Approximate computing has in recent years emerged as an important approach for energy saving mechanisms. Approximate computing involves reducing the number of transistors in a circuit to reduce delay and increase power savings. The power savings are at the cost of reduced accuracy. In most Signal Processing cases it is not necessary for the digital circuit to produce a precise output, the field...

VLSI Circuit Design is a significant subject for instance like adders and multipliers for the implementation of a various of logic and arithmetic functions likes of basic circuit approach and topology. Full adders like digital signal processors (DSP) architectures and microprocessors are vital elements in the application. Apart from that, the adding of two numbers is main assignment. it's key t...

This paper presents a comparative research of low-power and high-speed 4-bit full adder circuits. The representative adders used are a ripple carry adder (RCA) and a carry-lookahead adder (CLA). We also design a proposed carrylookahead adder (PCLA) using a new method that uses NAND gate for modification which helps in reducing the powerdelay product (PDP) for high performance applications. To y...

In this paper we propose a new 9 transistor 1-bit full adder. The proposed circuit performs efficiently in subthreshold region to employ in ultra low power applications. The main design objective for this new circuit is low power consumption and full voltage swing at a low supply voltage. The proposed cell also remarkably improves the power consumption, power delay product and has better noise ...

In digital CMOS design, power consumption has been a major concern for several years advanced IC fabrication technology allows the use of nano-scale devices so inability to get power to circuits, power leakage or to remove the heat they generate. By optimizing the transistor size in each stage power and delay can be minimized. This paper presents the analysis of full adders having efficient par...

Reversible logic circuits have found emerging attention in nanotechnology, quantum computing and low power CMOS designs. In this paper we present a modular synthesis method to realize a reversible Binary Coded Decimal (BCD) adder/subtractor circuit. We use genetic algorithms and don’t care concept to design and optimize all parts of a BCD adder circuit in terms of number of garbage inputs/outpu...

A performance analysis of 1-bit full-adder cell is presented. The adder cell is anatomized into smaller modules. The modules are studied and evaluated extensively. Several designs of each of them are developed, prototyped, simulated and analyzed. Twenty different 1-bit full-adder cells are constructed (most of them are novel circuits) by connecting combinations of different designs of these mod...

In recent year, power dissipation is one of the biggest challenges in VLSI design. Multipliers are the main sources of power dissipation in DSP blocks. In this project various types of full adders design are performed. Different techniques are used for low power in full adders. The design and power comparison of the low power multiplier using different types of full adder adders units are analy...

In this paper, five new multiplexer-based architectures for 1 -bit full adder circuit designs are proposed. Following these architectures, various full adder circuits can be built through different circuit implementations of multiplexers. For instance, in this paper, we demonstrate that by substituting each multiplexer with two transmission gates, a set of new full adder circuits are ready to b...