As we shrink down devices with technology scaling, process variation increases and it hinders SRAM VMIN scaling. Using peripheral assists, we can further lower the VMIN at the cost of energy and area. However, the SRAM VMIN varies with voltage, temperature and operating frequency variations, and it is hard to determine in real time. Prior work shows theoretically that canary SRAMs using reverse...

Multi-port memories are widely used as embedded cores in all communication System-on-Chip devices. Due to their high complexity and very low accessibility, Built-In Self-Test (BIST) is the most common solution implemented to test the different memories embedded in the system. This paper presents a programmable BIST architecture, based on a single microprogrammable BIST Processor and a set of me...

This paper describes the concept of a modular test code developed to reside in Microcontroller Units (MCUs) with Read-Only Memory (ROM) to make easier the test bench evaluation of integrated circuit (IC) prototypes designed at Brazil Semiconductor Technology Center (BSTC). MCU standard input/output ports are used to select independent operating modes and to transfer data from/to a hostcomputer....

This paper presents a strategy for testing future generations of wafer-level packaged logic devices that have nanoscale I/O structures. The strategy assumes that the devices incorporate built-in self test (BIST) features so that only a subset of the functional I/O needs to be directly accessed during testing. A miniature tester is described that provides test control, pattern sequencing, and cr...

Systems-on-Chip(SoC)s are now moving from logic dominant to memory dominant chips in order to satisfy high functionality and short development cycle. This means that the yield of memory part is the most important factor for the entire chip yield. In this paper, two word-oriented memory test algorithms are proposed newly. The one is an efficient writing NPSF test algorithm and the other is an ef...

In this paper we propose a novel built-in self-test (BIST) design for embedded SRAM cores. Our contribution includes a compact and efficient BIST circuit with diagnosis support and an automatic diagnostic system. The diagnosis module of our BIST circuit can capture the error syndromes as well as fault locations for the purposes of repair and fault/failure analysis. In addition, our design provi...

Memory-Built In Self-Test (MBIST) is an very effectual and output enrichment for embedded RAMs. This paper presents effectual MBIST concepts of Built-In-Self Test (BIST) using Performance Accelerator Algorithm (PAA). This BIST concept very stretchable for embedded RAMs with suitable operation. PA algorithm efficiently detects probable number of fault models compare to other March test algorithm...

The way integrated technology is growing becomes very difficult to apply circuit testing using Automatic TEST Equipment of complex circuit for this BIST (Built In Self test) is the solution of complex IC. Here we are applying BIST for UART which is considering as a low speed, low cost data exchange between computer and peripherals. Hence this paper shows implementation of UART with BIST capabil...

With increasingly stringent requirements for memory test, the complexity of the test algorithm is increasing. This will make BIST (Build-In-Self-Test) circuit more complex and the area of BIST circuit larger. This paper proposes a novel controllable BIST circuit. The controllable BIST circuit provides a cost-effective solution that supports a variety of March algorithms and SRAM embedded testin...

ÐThis paper presents an integrated approach for both built-in online and offline testing of embedded DRAMs. It is based on a new technique for output data compression which offers the same benefits as signature analysis during offline test, but also supports efficient online consistency checking. The initial fault-free memory contents are compressed to a reference characteristic and compared to...