Abstract In this paper, a novel super-junction (SJ) MOSFET with enhanced switching performance and ruggedness is proposed investigated by the method of TCAD simulations. An N + /P - polysilicon junction gate electrode separation layer between P-base P-pillar are introduced to trench SJ-MOSFET. For gate, P located in bottom plays role insulating layer, which efficiently reduces charge (Q G ), th...

The long links that interconnect networking and computing systems and boards need high throughput to avoid expensive, massively parallel connections. However, long wires suffer signal losses that increase with frequency. Digital communication techniques can compensate for these losses, but require Analog-to-Digital and Digital-to-Analog converters (ADCs and DACs). To understand the application ...

In this paper a study of the noise performance of electret microphone systems as a part of hearing aids is presented. The signalto-noise ratio of the microphone-preamplifier combination, containing a field-effect transistor (FET) and a high value resistive bias element in a hybrid configuration, is mainly determined by the noise generated in the preamplifier circuit. A theoretical analysis of t...

The maximum speed of synchronous circuits is generally constrained by the worst case propagation delay, which limits the system clock frequency. Various techniques exist to manage the circuit delay, trading off speed for other system resources. One such approach is to equalize the rise and fall delay times. The primary design parameter for equalizing these delay times is the ratio between the w...

Device miniaturization is an important part of VLSI design, which refers to reduction in dimension of device by keeping all other characteristic constant. As technology node is moving in submicron region, the performance of the device degrades due to short channel effects and narrow channel effects. The key issues due to these effects are draininduced-barrier– lowering (DIBL), leakage current, ...

A SPICE (simulation program with integrated circuit emphasis) model for a single-electron transistor (SET) was developed based on the physical phenomena in realistic Si SETs and was implemented into a conventional circuit simulator. In the proposed model, the SET current calculated using an analytic model is combined with the parasitic MOSFET (metal-oxide semiconductor field effect transistor) ...

A partial silicon on insulator (PSOI) is a widely recognized technology suitable for high-voltage (HV) architectures power integrated circuits (PICs). Despite the added process complexity compared with SOI reduced surface field (RESURF), this offers wider range of voltage ratings due to action depletion layer in handle wafer (HW), parasitic capacitances extra volume region HW, and better heat c...

The long links that interconnect networking and computing systems and boards need high throughput to avoid expensive, massively parallel connections. However, long wires suffer signal losses that increase with frequency. Digital communication techniques can compensate for these losses, but require Analog-to-Digital and Digital-to-Analog converters (ADCs and DACs). To understand the application ...

Accuracy of timing in circuits and systems using nanoscale transistors is crucial and is dependent, to first order, on the capacitances of the load transistors. It is accepted that variation in parameters will be intrinsic to such devices due to, among other factors, the discrete nature of the doping. It is likely that one such parameter exhibiting variation will be capacitance. Here we investi...