In this paper, we review the 1/f-type noise properties of nanoelectronic devices focusing on three demonstrative platforms: resistive switching memories, graphene nanogaps and single-molecule nanowires. The functionality such ultrasmall is confined to an extremely small volume, where bulk considerations loose their validity: relative contribution a fluctuator heavily depends its distance from d...

We demonstrate a dark-field microscopic technique for real-time monitoring of DNA metallization. The growth of silver nanoparticles on DNA molecules was observed using plasmon resonance light scattering in the presence of a weak catalyst triggering photo-reduction of Ag(+). This simple strategy could facilitate the controlled fabrication of DNA-templated nanoelectronic devices.

We present the direct observation, using off-axis electron holography (EH), of the electric potential distribution in the vicinity of a single carbon nanotube electrically biased by two closely spaced contacts. When our results are combined with finite element modeling, we demonstrate the ability to separately observe the electrostatic potential drops across the metal contacts at the interface ...

This paper surveys and explains nanometer-scale, quantum-effect alternatives to micron-scale, bulk-effect transistors in digital circuits. The status of R&D and recent important advances are reviewed briefly.

Nanodevices based circuit design will be based on the acceptance that a high percentage of devices in the design will be defective. In this work, we investigate a defect tolerant technique that adds redundancy at the transistor level and provides built-in immunity to permanent defects (stuck-open, stuck-short and bridges). The proposed technique is based on replacing each transistor by N 2 -tra...

Neuromorphic networks of high connectivity may be implemented using CMOS circuits as cell bodies, nanowires as axons and dendrites, and self-assembled single-molecule latching switches as synapses. The integration scale of such “CrossNet” circuits of acceptable size (~30×30 cm2) may be comparable with that of the mammal’s cerebral cortex (up to 1010 neurons), despite the quasi-2D structure of t...

We have calculated the minimum chip area overhead, and hence the bit density reduction, that may be achieved by memory array reconfiguration (bad bit exclusion), combined with error correction code techniques, in prospective terabit-scale hybrid semiconductor/nanodevice memories, as a function of the nanodevice fabrication yield and the micro-to-nano pitch ratio. The results show that by using ...