This paper presents some new extensions of our Mathematica toolbox Analog Insydes for modeling and analysis of nonlinear circuits. Circuits are described by means of hierarchical netlists containing top-level netlists, subcircuits, and symbolic device model descriptions from which circuit equations can be set up in sparse tableau or modified nodal formulation. Some examples of Analog Insydes’ n...

The design of programmable logic architectures and supporting computer-aided design tools fundamentally requires both a good understanding of the combinatorial nature of netlist graphs and sufficient quantities of realistic examples to evaluate or benchmark the results. In this paper, the authors investigate these two issues. They introduce an abstract model for describing sequential circuits a...

In this paper, we present an eecient Iterative Improvement based Partitioning (IIP) algorithm called LSR/MFFS, that combines signal ow based Maximum Fanout Free Sub-graph (MFFS) clustering algorithm with Loose and Stable net Removal (LSR) partitioning algorithm. The MFFS algorithm generalizes existing MFFC decomposition method from combinational circuits to general sequential circuits in order ...

We examine the utility of the Large-Step Markov Chain (LSMC) technique [13], a variant of the iterated descent heuristic of Baum [2], for VLSI netlist bipartitioning. LSMC iteratively nds a local optimum solution according to some greedy search (in our case, the Fiduccia-Mattheyses heuristic) and then perturbs this local optimum via a \kick move" into the starting solution of the next greedy de...

Many partitioning algorithms have been proposed for distributed Very-large-scale integration (VLSI) simulation. Typically, they make use of a gate level netlist and attempt to achieve a minimal cutsize subject to a load balance constraint. The algorithm executes on a hypergraph which represents the netlist. We propose a design-driven iterative partitioning algorithm for Verilog based on module ...

The demand for decreased turn around time in the design of programmable digital circuits requires CAD tools for synthesis, veri cation and code generation. Usually a RT level netlist is available as soon as the datapath is designed. Given the netlist and the behavior of the RT level modules, the proposed compiler maps a source program to the binary code of the target machine. The main tasks of ...

Automatic formal verification techniques generally require exponential resources with respect to the number of primary inputs of a netlist. In this paper, we present several fully-automated techniques to enable maximal input reductions of sequential netlists. First, we present a novel min-cut based localization refinement scheme for yielding a safely overapproximated netlist with minimal input ...

Triple Modular Redundancy (TMR) is a common technique to protect memory elements for digital processing systems subject to radiation effects (such as in space, high-altitude, or near nuclear sources). This paper presents an approach to verify the correct implementation of TMR for the memory elements of a given netlist (i.e., a digital circuit specification) using heuristic analysis. The purpose...

Silvaco’s Guardian LVS tool compares two circuits that are defined by their netlists. The comparison is based strictly on the topological structure of these circuits. Topologically equivalent netlists are considered different, even if they are functionally equivalent. There are several techniques available for designing the same functionality by means of topologically different netlists. While ...

in 2003, waters, felten and sahai introduced a novel cryptographic primitive called incomparable public key cryptosystem to protect anonymity of message receivers in an untrusted network. in this setting, a receiver is allowed to create many anonymous identities for himself without divulging the fact that all these identities refer to the same receiver. recently, lee and lim improved the soluti...