111 this paper, a new architecture called the extendable instruction set computer (EISC) is introduced that addresses the issues of memory size and performance in embedded microprocessor systems. The architecture exhibits an efficient fixed length 16-bit instruction set with short length offset and immediate operands. The offset arid imniediate operands can be extended to 32 bits via the operat...

Adders are crucial logical building blocks found almost in all the modern electronic system designs. In adder architecture design, fundamental issue is propagation latency carry chain. As length of input operands increases, chain along with it. Parallel prefix adders, which address problem most efficient topologies for hardware implementation. However, delay reduction still could be achieved ve...

The Montgomery inversion is a fundamental computation in several cryptographic applications. In this work, we propose a scalable hardware architecture to compute the Montgomery modular inverse in GF(p). We suggest a new correction phase for a previously proposed almost Montgomery inverse algorithm to calculate the inversion in hardware. The intended architecture is scalable, which means that a ...

Operand bypass logic is likely to be one of the critical structures for future microprocessors to achieve high clock speed. The logic delay causes the execution time budget to be reduced significantly, so that the execution stage is divided into several stages. The variable latency pipeline (VLP) structure has the advantages of pipelining and pseudo-asynchronous design. According to the source ...

Parity helps us determine whether an arithmetic equation is true or false. The current research examines the development of sensitivity to parity cues in multiplication in typically achieving (TA) children (grades 2, 3, 4 and 6) and in children with mathematics learning disabilities (MLD, grades 6 and 8), via a verification task. In TA children the onset of parity sensitivity was observed at th...

This paper presents a new design for two operand normalization. The two operand normalization operation involves the normalization of at least one of two operands by left shifting both by the same amount. Our design performs the computation of the shift by making an OR of the bits of both operands in a tree network, encoding the position of the first nonzero bit. The encoded position is obtaine...

Horizontal collision correlation analysis (HCCA) imposes a serious threat to simple power analysis resistant elliptic curve cryptosystems involving unified algorithms, for e.g. Edward curve unified formula. This attack can be mounted even in presence of differential power analysis resistant randomization schemes. In this paper we have designed an effective countermeasure for HCCA protection, wh...

This paper describes how to implement efficient FIR filters on ARM Cortex-M3 microprocessors. Two multiply-accumulate instructions are discussed: MLA – multiply with accumulate, using 32-bit operands and producing a 32-bit result, and SMLAL – signed multiply with accumulate, using 32-bit operands and producing a 64-bit result. There are advantages and disadvantages for each instruction. It is p...

We describe a software tool for performing automatically veri ed arithmetic operations on independent operands when the operands are intervals, or probability distribution functions, or one operand is an interval and the other is a distribution. Intervals and distributions are expressed using the same technique, so the algorithms do not need to distinguish between intervals and distributions in...