In a high level synthesis environment there is a strong need for flexible module generators. For the generation of regular structures efficient dedicated module generators can be built. This paper describes the structure of a ’block– multiplier’, which features a wide range of area–time tradeoffs maintaining efficiency. The structure makes it possible to implement a fully serial or a fully para...

Braun multiplier is one of the parallel array multipliers, which is used for unsigned numbers multiplication. This paper presents different techniques for optimizing the multiplier in power and delay parameters. The dynamic power of a multiplier can be reduced by using bypassing techniques and delay can be reduced by replacing ripple carry adder in the last stage of full adders by optimized add...

A redundant binary (RB) representation is used for designing high performance multiplier. Because of its high modularity and carry free addition. The error correcting word (ECW) plays an important role in redundant binary multiplier. The redundant binary (RB) coding and modified booth (MB) encoding creates the error correcting word. The extra error correcting is eliminated by combining the erro...

A Montgomery’s algorithm in GF(2) based on the Hankel matrix–vector representation is proposed. The hardware architecture obtained from this algorithm indicates low-complexity bit-parallel systolic multipliers with irreducible trinomials. The results reveal that the proposed multiplier saves approximately 36% of space complexity as compared to an existing systolic Montgomery multiplier for trin...

This paper presents, low power signed and unsigned fixed-width multipliers using the column bypassing technique with carry save adder array structure. We have decomposed the partial products into two parts and executed them in parallel to reduce the delay of proposed fixed-width array multiplier. The proposed multiplier reduces the power consumption by skipping the unwanted switching activity w...

A hybrid radix-4/radix-8 architecture targeted for high bit, general purpose, digital multipliers is presented as a compromise between the high speed of a radix-4 multiplier architecture and the low power dissipation of a radix-8 multiplier architecture. In this hybrid radix4/radix-8 multiplier architecture, the performance bottleneck of a radix-8 multiplier, the generation of three times the m...

A new bi-directional bit serial-parallel multiplication architecture is presented. The proposed structure is regular and modular, and requires nearest neighbour communication links only, which makes it more efficient for VLSI implementation. Furthermore, a judicious deployment of larches in the circuit ensures that the multiplier operates on two coefficients of the multiplicand at the same time...

Booth encoded Multiplier is used to reduce the hardware utilization in chip level designing in VLSI projects. The present project is focusing on designing and developing a powerful Booth encoded multiplier integrated with Carry Select Adder [CSLA]. Primarily the on hand Booth encoding multiplier is used in multiplication operations based on signed numbers only. The multipliers such as braun arr...

AbscrocrWe present a mixed-signal distributed VLSI architecture for massively parallel array processing, with fine-grain embedded memory. The three-transistor processing element in the array combines a charge injection device (CID) binary multiplier and analog accumulator with embedded dynamic random-access memory (DRAM). A prototype 512 x 128 vector-matrix multiplier on a single 3 mm x 3 mm ch...