Ezafe construction is an idiosyncratic phenomenon in the Persian language. It is a good indicator for phrase boundaries and dependency relations but mostly does not appear in the text. In this paper, we show that adding information about Ezafe construction can give 4.6% relative improvement in dependency parsing and 9% relative improvement in shallow parsing. For evaluation purposes, Ezafe tags...

A system for the measurement of accelerometer shock sensitivity is described, complying with the requirements of comparison calibration per ISO 16063-22 “Methods for the calibration of vibration and shock transducers Part 22: Shock calibration by comparison to a reference transducer”. This system is comprised of a newly designed exciter, a new back-to-back comparison standard with integral char...

Ali K. Nahar University of Technology, Department of Electrical Engineering Abstract A first order of DWA (data weighted averaging) technique is proposed to improve 6-bit digital-to-analog convertor (DAC). In addition, this paper discusses the impact of mismatch between DAC unit elements. The simulation results show the effectiveness of the DWA technique in reduction of inband tones, also DWA t...

A synthesiser has been designed for polyphonic (multivoice) singing synthesis. Singing synthesis requires frequent updating of parameters to achieve a natural output sound. These parameters include fundamental frequency, formant frequencies, formant bandwidths, and voice source parameters (such as Open Quotient). The synthesis engine is controlled using a script and a graphical user interface. ...

This research presents the review of Analog to Digital Convertor (ADC). For ADC there are mainly four different methods, Flash ADC, Pipelined ADC, Successive Approximation ADC, and Sigma Delta ADC. The Flash ADC is the Fast ADC. For Designing the ADC, the parameters important are Static and Dynamic. In static parameters Differential Non Linearity Error (DNLE), Integral Non Linearity Error (INLE...

In Analog to digital convertor design converter, high speed comparator influences the overall performance of Flash/Pipeline Analog to Digital Converter (ADC) directly. This paper presents the schematic design of a CMOS comparator with high speed, low noise and low power dissipation. A schematic design of this comparator is given with 0.18μm TSMC Technology and simulated in cadence environment. ...

The need for ultra low-power, area efficient and high speed analog-to-digital converters is pushing toward the use of dynamic regenerative comparators to maximize speed and power efficiency. The objective of this paper is to design and implementation of delay efficient and low power consumption double-tail dynamic comparator in successive approximation analog to digital convertor. The conventio...

with increase in traffic and speed railway became one of the major load on supply grid .AC-DC convertor used in locomotive of traction system draws rich harmonics content current results in poor power quality and failure or missed operation of utility causing derating of grid and affect the reliability. This paper provide framework for issue like harmonics, voltage sage ,voltage unbalance, poor...