This paper introduces Explicit Dynamic Scheduling (EDS), a practical implementation of dataaow on a chip. By combining RISC design principles with well-known compiler dependence analysis techniques, EDS combines a straightforward hardware design, suitable for high speed implementation, with the performance advantages of dataaow at the instruction level. EDS uniies pipeline and memory latency to...

The problem of scheduling parallel applications on Grids is notoriously difficult: schedulers must consider the heterogeneity of involved resources and management systems, and they often require the users to provide information about the expected application behavior. We suggest that increasingly popular structured programming approaches, using components with well-defined semantics, facilitate...

In this paper, we propose new pipelined request-grant-accept (RGA) and request-grant (RG) maximal size matching (MSM) algorithms to achieve speedup in combined input and output queueing (CIOQ) switches. To achieve a speedup factor , in the proposed pipelined RGA/RG MSM algorithms, we pipeline operations of finding matchings in scheduling cycles based on the observation that all matched inputs/o...

A supply chain encompasses several agents, such as vendors, wholesalers, manufacturers, retailers and customers. These companies must share information and coordinate physical execution to ensure a smooth flow of goods, services, information, and cash through the pipeline. Collaboration among entities in the supply chain can have a positive impact on the system performance. In this context, the...

K – Survey of Instruction Set Architectures related to instruction-, data-, thread-, and requestlevel parallelism necessary for understanding Loop unrolling. ILP, Compiler techniques to increase ILP. Register Renaming, Pipeline Scheduling, Loop Unrolling. Conclusion. CPE 731, ILP. 3. Instruction Level Parallelism. 5 Optimizing Program Performance(Loop Unrolling and Enhancing Parallelism ) Michael.

Loop pipelining is an important optimization in high-level synthesis (HLS) because it allows successive loop iterations to be overlapped during execution. While current HLS pipelining approach achieves high performance for loops with regular and statically analyzable program patterns, it remains challenging to pipeline loops with irregular memory accesses, irregular dependence patterns, and unb...

This paper presents a novel approach to aid the operational decision-making of scheduling activities in a real-world pipeline, transporting heavy oil derivatives, which are products of less aggregate value, such as fuel oils, e.g. marine fuel. These products present special characteristics that influence their transport as the impossibility of being transferred at room temperature, due to their...

The MapReduce programming model is widely acclaimed as a key solution to designing data-intensive applications. However, many of the computations that fit this model cannot be expressed as a single MapReduce execution, but require a more complex design. Such applications consisting of multiple jobs chained into a long-running execution are called pipeline MapReduce applications. Standard MapRed...

Pipeline execution is a form of parallelism in which subcomputations of a repeated computation, such as statements in the body of a loop, are executed in parallel. A measure of the execution time of a pipeline is needed to determine if pipelining is an effective form of parallelism for a loop, and to evaluate alternative scheduling choices. We derive a formula for precisely determining the asyn...

This paper presents a framework for a reconfigurable computing system, consisting of cohesive hardware and software architectures. The framework allows customization of the hardware and software to fit a class of applications, while narrowing the design space to a manageable set of design parameters. The framework features a novel hybrid static and dynamic pipeline scheduling technique, which d...