Classical scheduling approaches are applied here to overcome the problem of unequal-length block-test scheduling under power dissipation constraints. List schedulinglike approaches are proposed j r s t as greedy algorithms to tackle the fore mentioned problem. Then, distributiongraph based approaches are described in order to achieve balanced test concurrency and test power dissipation. An exte...

1 A preliminary version of this work has appeared in Proceedings of ASP-DAC 2003. ABSTRACT Leakage power and hot-carrier effects are emerging as key concerns in deep sub-micron CMOS technologies with respect to their effects on the total power dissipation and reliability of VLSI circuits. Leakage power dissipation is rapidly becoming a substantial contributor to the total power dissipation as t...

we have applied the method of integration of the heisenberg equation of motion proposed by bender and dunne, and m. kamella and m. razavy to the potential v(q) = v q - µ q with linear and nonlinear dissipation. we concentrate our calculations on the evolution of basis set of weyl ordered operators and calculate the mean position , velocity , the commutation relation [q, p], and the energy of pa...

This paper explores the deterministic transistor reordering in low-voltage dynamic BiCMOS logic gates, for reducing the dynamic power dissipation. The constraints of load driving (discharging) capability and NPN turn-on delay for MOSFET reordered structures has been carefully considered. Simulations shows significant reduction in the dynamic power dissipation for the transistor reordered BiCMOS...

Voltage scaling has been often used for reducing power dissipation of CMOS driven interconnects. An undesired effect observed due to voltage scaling is increase in propagation delay. Thus a trade off lies between power dissipation and propagation delay with voltage scaling. However, voltage scaling can result in overall reduction of power delay product (PDP). Therefore, their lies an optimized ...

Now-a-days leakage power is an important issue in microprocessor’s and hardware’s. In modern computer systems memory components covers 70 to 80 percent of total area of microprocessors that means memory contains more number of transistors. Generally leakage power dissipation proportional to the number of transistors. So the leakage power dissipation is more in the memories. In high performance ...

The main aim of this paper is to design and implement efficient UART and test the UART with built in self testing technique . A new Test pattern generator is simulated and used in BIST architecture in order to reduce power dissipation. As we know that power dissipation is more during the test mode than in normal mode hence In this project the pattern generator used is the low power pattern gene...

In this paper, we discuss on accuracy of power dissipation models for CMOS VLSI circuits. Some researchers have proposed several e cient power estimation methods for CMOS circuits [1][2][3][4]. However, we do not know how accurate they are because we have not established a method to compare the estimated results of power consumption with power consumption of actual VLSI chips. To evaluate the a...