MlPS is an 32-bit, high pcrformancc processor architecture implcmcntcd as an nMOS VLSI Gp. I'hc processor uses a low 1~~1, strcamlincd instruction set coupled \vit!l a fast pipeline to achicvc an instruction rate of two million instructions per second. Close interaction bctwccn the processor dcsigll and car-npilzrs for the machine yields cfficicnt execution of programs on the chip. Simplifyin g...

Application-specific circuits are used to migrate computer systems from workstations to handheld devices that need real-time performance within the budget for physical size and energy dissipation. However, these circuits are inflexible as any modification requires redesign and refabrication, which is both expensive and time-consuming considering the complexity of recent embedded platforms. Ther...

This paper presents SmartCell, a novel coarse-grained reconfigurable architecture, which tiles a large number of processor elements with reconfigurable interconnection fabrics on a single chip. SmartCell is able to provide high performance and energy efficient processing for stream-based applications. It can be configured to operate in various modes, such as SIMD, MIMD, and systolic array. This...

For my MSc project at the Computer Engineering Laboratory at Delft University of Technology I will design and implement a reconfigurable Very Large Instruction Word (VLIW) processing core, for use within the Molen[6, 9] reconfigurable processing paradigm. The Instruction Set Architecture (ISA) used for this processing core will be VEX[2] (VLIW Example), which is loosely modeled on the ISA of th...

This paper represents the combination of Reduced Instruction Set Computer (RISC) system using VHDL and implement. This paper presents a RISC processor designing to achieve various arithmetic operations. The RISC is a 20 bit processor. KeywordsArithmetic Logic(AL), Central Processing Unit(CPU), Control Unit(CU), Field Programmable Logic Array(FPGA), General Purpose Register(GPR), Program Counter...