Although CMOS Time-of-Flight Range Image Sensors have been recently realized, the fabrication process is modified by inserting an extra mask layer to allow efficient TOF dependent charge transfer. This work focuses on the selection procedure of amplifiers to be used in the design of the TOF pixel using the standard CMOS process. From our analysis, it is found that the Cascode amplifier is the b...

In this work, a detailed comparison of four equivalent charge-sensitive, folded-cascode amplifiers in terms of noise performance is presented. A couple of complementary structures, one with a noise-optimised input nMOSFET and the other with a noise-optimised input pMOSFET were designed in 0.35 μm CMOS process by Austria MicroSystems (AMS). Another couple of complementary structures consisting o...

Three circuit techniques are proposed that provide (with simultaneous use) an increase bymore than two orders of magnitude the maximum output voltage slew rate (SR) microelectronicoperational amplifiers (op-amps) based on bipolar transistors with a classical architecture,designed to operate in automatic control systems, radio engineering and communications, forexample, as drivers for ultra-high...

In this paper, a low Power, Gain Boosted Recycling Folded Cascode Operational Transconductance Amplifier (GB-RFC OTA) is described. The proposed GB-RFC OTA is designed using 130nm CMOS technology and achieves enhanced gain, unity gain bandwidth and slew rate with the low Power budget. The proposed circuit operates on 1V supply voltage and 200 μA bias current and consumes a power of 798μW.The GB...

First, we create a MOS-NDR (negative differential resistance) cell and then put two MOS-NDR cells in cascode (totem-pole) structure. With MOBILE (monostable-bistable transition logic element) theorem we can built a MOS-NDR inverter by placing a NMOS in parallel with the lower part of the cascode structure. The MOS-NDR inverter cascades two Common-Source amplifier and feedback to MOS-NDR inverte...

Low voltage (LV) analog circuit design techniques are addressed in this tutorial. In particular, (i) technology considerations; (ii) transistor model capable to provide performance and power tradeoffs; (iii) low voltage implementation techniques capable to reduce the power supply requirements, such as bulk-driven, floating-gate, and self-cascode MOSFETs; (iv) basic LV building blocks; (v) multi...

This paper presents a new common-mode stabilization method for a CMOS differential cascode Class-E power amplifier with LCtank based driver stage. The stabilization method is based on the identification of the poles and zeros of the closed-loop transfer function at a critical node. By adding a series resistor at the common-gate node of the cascode transistor, the right-half-plane poles are move...

A low noise amplifier has been designed using a 2SK117 N channel J-FET as the input device in a cascode [1] configuration. Noise measurements on this amplifier yield a low frequency noise current of 0.25 fA/Yfu and a voltage noise of less than 1.2 n V NHz in the 500 Hz to 50 kHz region. Bloyet et al. [2] suggest a figure of merit of the product of the noise voltage and current as being appropri...

A fully-differential seventh-order 0.05° equiripple linear phase low-pass filter based on multiple loop feedback (MLF) leapfrog (LF) topology is presented for read/write channels. The filter is designed and simulated with the proposed fully balanced, highly linear operational transconductance amplifier (OTA). This OTA contains two complementary differential cross-coupled input pairs and a pair ...

In this study an ultra-broad band, low-power, and high-gain CMOS Distributed Amplifier (CMOS-DA) utilizing a new gain-cell based on the inductively peaking cascaded structure is presented. It is created bycascading of inductively coupled common-source (CS) stage and Regulated Cascode Configuration (RGC).The proposed three-stage DA is simulated in 0.13 μm CMOS process. It achieves flat and high ...