The radio-frequency (rf) performance of a 0.18m CMOS logic technology is assessed by evaluating the cutoff and maximum oscillation frequencies ( and max) the minimum noise figure ( min) and associated power gain ( ) and the 1/ -noise of the devices. Gate-biasing and channel-length and gate-finger-length adjustments are identified as means to optimize the rf performance without any technology pr...

For extremely-scaled CMOS technologies, supply voltages well below 1V will be required to maintain reliability [1]. Analog and RF design with standard devices then becomes very challenging because of the significant reduction in both the available signal swing and the available overdrive for biasing. We present ultralow-voltage design techniques that maintain all node voltages between the suppl...

Voltage controlled oscillators are essential building blocks in communication systems and are used as local oscillators to up and down-convert signals in an RF mixer. Despite the continuous improvement in the state of the art of CMOS VCO’s, they still remain the most critical blocks of RF transceivers. The most important parameters of a VCO are phase noise, power consumption and frequency tunin...

An optimum OTA topology is done in order to optimize MOS transistor sizing.Also, the design of folded cascode OTA, which works for frequencies that lead to a base band circuit design for RF application, is based on transistor sizing methodology. Simulation results are performed using SPICE software and BSIM3V3 model for CMOS 0.18μm process, show that the designed folded cascode OTA has a 52dB D...

The design of analog and radio-frequency (RF) circuits in CMOS technology becomes increasingly more difficult as device modeling faces new challenges in deep submicrometer processes and emerging circuit applications. The sophisticated set of characteristics used to represent today’s “digital” technologies often proves inadequate for analog and RF design, mandating many additional measurements a...

In this paper, we have analyzed the Double-Pole Four-Throw Double-Gate Radio-Frequency Complementary Metal-Oxide-Semiconductor (DP4T DG RF CMOS) switch using S-parameters for 1 GHz to 60 GHz of frequency range. DP4T DG RF CMOS switch for operation at high frequency is also analyzed with its capacitive model. The results for the development of this proposed switch include the basics of the circu...

A highly linear down conversion mixer with moderate gain used for 2.4GHz RF applications is presented in this paper using 0.18μm CMOS technology. The proposed mixer incorporates current bleeding technique & degenerative resistors to improve linearity and conversion gain. Also the negative feedback configuration of the circuit gives flat conversion gain increasing the overall bandwidth. The simu...

A 2.4 GHz CMOS RF front-end using for ZigBee application is described. The front-end consists of a low noise amplifier and a down-mixer and uses a 2 MHz IF frequency. A common source with resistive feedback and an inductive degeneration are adopted for a low noise amplifier, and a 20 dB gain control step is digitally controlled. A passive mixer for low current consumption is employed. The RF fr...

This paper presents a 30dBm (1W) class-E power amplifier projected in a standard 0.18-μm CMOS technology. The power amplifier (PA) consists in two differentials stages. The main stage employs a cascode class-E RF power amplifier with a self-biasing circuit. The driver stage uses the technique of Injection-Locking to substantially reduce the input power signal, maintaining a high gain. At 2.45 G...

In this paper substrate network resistances are analyzed and extracted for multi-finger MOS transistors used in RF applications. The commonly used model for MOS transistors in RF applications mainly consists of a substrate resistance network having three resistors. A typical horse-shoe CMOS transistor laid out and all substrate resistances are extracted from I-V characteristics. Device and proc...