Pulse-triggered flip-flops are mainly used to improve speed of operation (pipeline speed), though flip-flop robustness and system timing closure are challenging in a wide range of supply voltages. Usually pulse-triggered flip-flops have specific structures and transistor sizes to optimize the system performance. The transistor size, topology, and threshold voltage of the flip-flop make the timi...

The consumption of power has become an important issue in modern VLSI design. Power consumption can be reduced by replacing some flip-flops with fewer multi-bit flip-flops. Multi-bit flip-flop is one of the methods for clock power consumption reduction. This project focuses on reduction of power using multi-bit flipflops by clock synchronization. Two single bit flip-flops are synchronized with ...

In this paper, we propose a novel Low-Power Dual dynamic node and edge triggered (DDNET) flip flop for Featuring Efficient low power applications. Several art of design techniques have been proposed to eliminate large capacitance in the precharge node of the conventional flip-flop, which drives separately by output pull-up, and pull down transistors. Though the pioneer designs which consumes mu...

In this paper a new technique is proposed based on the comparison between Conventional Transistorized Flip-flop and Data transition Look ahead D flip flop here we are checking the working of DLDFF and the conventional D Flip-flop after that we are analyzing the characteristic comparison using power & area constraints after that we are proposing a Negative Edge triggered flip-flop named as Switc...

BACKGROUND Flip-flops are an item of footwear, which are rubber and loosely secured across the dorsal fore-foot. These are popular in warm climates; however are widely criticised for being detrimental to foot health and potentially modifying walking gait. Contemporary alternatives exist including FitFlop, which has a wider strap positioned closer to the ankle and a thicker, ergonomic, multi-den...

Context. The IUE database provides a large number of UV high and low-resolution spectra of RS CVn-type stars from 1978 to 1996. In particular, many of these stars were monitored continuously during several seasons by IUE. Aims. Our main purpose is to study the short and long-term chromospheric activity of the RS CVn systems most observed by IUE: HD 22468 (V711 Tau, HR 1099, K1IV+G5V), HD 21242 ...

In Integrated circuits a gargantuan portion of on chip power is expended by clocking systems, which comprises of timing elements such as flip-flops, latches and clock distribution network. These elements absorb approximately 30% to 60% of the total power dissipation in the system. In order to design high performance and power efficient circuits a scrupulous approach should be adopted to reduce ...

System on chip (SOC) design integrates many complex modules in one chip. As number of modules per chip is increasing, number of transistors in a chip increases resulting in increase in area and power dissipation. Area and power dissipation problems can be most effectively addressed if the basic building blocks of the circuit are designed for lower power dissipation and occupy less space. Flip-F...

The paper proposed a new design for implementing semi-static flip-flop for low power and high performance applications. In this work, comparative analysis of six existing flip-flop designs along with the proposed design is made. The proposed design has better power, delay and PDP than the existing architectures. All simulations are performed on TSpice using BSIM models in 130 nm process node. T...