John Trono published a new exercise in concurrent programming—the Santa Claus problem—and provided a solution based on semaphores [12]. His solution is incorrect because it assumes that a process released from waiting on a semaphore will necessarily be scheduled for execution. We give a simple solution in Ada 95 using higher order synchronization primitives: protected objects and rendezvous. We...

A graphical form of the mutual exclusion problem is considered in which each vertex represents a process and each edge represents a mutual exclusion constraint between the critical sections of the processes associated with its endpoints. An edge semaphore solution for mutual exclusion problems is defined, and those graphs which are edge solvable are characterized in terms of both a forbidden su...

We investigate the performance of barrier syn-chronisation on both shared-memory and distributed-memory architectures, using a wide range of techniques. The performance results obtained show that distributed-memory architectures behave predictably, although their performance for barrier synchronisation is relatively poor. For shared-memory architectures, a much larger range of implementation te...

Using priority inheritance protocols is an e ective approach to solve the problem of uncontrolled priority inversion, which is among the major sources of deadline violations in hard real-time systems. In this paper, some approaches to incorporate priority inheritance to the ITRON speci cation are discussed. As the result, we propose two speci cations of priority inheritance semaphore functions ...

Modern embedded markets call for high density computing ability, making it is difficult to use just one microprocessor to meet function requirements of highperformance embedded systems. Multiple processors, including general-purpose embedded microprocessors, digital signal processors (DSPs), ASICs and FPGA hardware accelerators, are often used in these embedded systems. Not all processors in an...

In this paper we present a novel parallel arithmetic architecture using an efficient non-binary logic scheme. We show that by using parallel broadcasting (or domino propagating) state signals, on short reconfigurable buses equipped with a type of switches, called GP (generate-propagate) shift switches, several arithmetic operations can be carried out efficiently. We extend a recently proposed s...

This paper describes a multiprocessor machine for real-time Digital Signal Processing that uses commercial pro-grammable DSP chips. The architecture is a shared memory , single shared bus parallel processor designed to run signal processing tasks that can be statically scheduled. Compile time information inherent in such applications is used to constrain an order in which shared resources are a...

Concurrent access to shared data in preemptive multi-tasks environment and in multi-processors architecture have been subject of many works. Proposed solutions are commonly based on semaphores which have several drawbacks. For many cases, lock-free techniques constitute an alternate solution and avoid the disadvantages of semaphore based techniques. We present the principle of these lock-free t...