Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach to generating compact test sequences for sequential circuits. Our approach combines a conventional ATPG algorithm, a technique based on the frozen clock testing strategy, and a dynamic compaction method based on a genetic algorithm. The frozen clock strategy temporarily suspends...

| In this paper, we theoretically and experimentally show the e ectiveness of partial scan design based on internally balanced structure, which is a sequential circuit capable of generating tests with a combinational test generation algorithm. Moreover, we introduce a method of extended partial scan design, which replaces part of not only ipops by scan ipops but also wires by bypass ipops in a ...

Partial reset has been shown to have significant impact on deterministic test generation for sequential circuits. In this paper, we explore the use of partial reset in fault-independent testing and application to built-in selftest. We take the following approach: based on fault propagation analysis, we select a subset of the circuit flip-flops to be initialized to 0 or 1. The initialization (se...

Sequential circuit fault simulators use the multiple bits in a computer data word to accelerate simulation. We introduce, and implement, a new sequential circuit fault simulator, a parallel pattern parallel fault simulator, ZAMBEZI, which simultaneously simulates multiple faults with multiple vectors in one data word. ZAMBEZI is developed by enhancing the control ow of existing parallel pattern...

The action system framework for modelling parallel programs is used to formally specify a microprocessor. First the microprocessor is specied as a sequential program. The sequential specication is then rened into a concurrent program using correctness-preserving program transformations. Previously a similar derivation was carried out informally within the CSP-framework at Caltech, where also a ...

We present a new approach to automatic test pattern generation for very large scale integrated sequential circuit testing. This approach is more eecient than past test generation methods, since it exploits knowledge of potential circuit defects. Our method motivates a new combinatorial optimization problem, the Tour Covering Problem. We develop heuristics to solve this optimization problem, the...

Retiming is a transformation that optimizes a sequential circuit by relocating the registers. When the circuit has an initial state, one must compute an equivalent initial state for the retimed circuit. In this paper we propose a new efficient retiming algorithm for performance optimization. The retiming determined by the algorithm is the best with respect to initial state computation. It is th...

Scan paths are commonly used in digital design to improve the testability of sequential circuits since a full scan path provides complete controllability and observability for every bistable element. A traditional scan path is implemented after the circuit has been designed, with little regard to the actual circuit function. High-level synthesis can exploit knowledge of the circuit function to ...

This paper presents a new method for designing asynchronous sequential circuits. The inspiration for this method is derived from the traditional synchronous design method. We introduce a new component which is used as a building block for sequential parts of asynchronous circuits. This new component is similar to the old Flip-Flop but it has the ability to handle signal edges asynchronously. Th...

We present a high-performance circuit style that mitigates transient noise such as logic soft errors. Two most significant contributions of this work are: (1) a new design paradigm that addresses the tradeoff between performance and reliability by balancing the design of high-speed combinational logic circuit and that of transient-tolerant sequential element, and (2) a new testing scheme that e...