Bit-serial architectures require less area but more sophisticated clocking mechanisms than their parallel counterparts. This paper presents a CMOS circuit that generates high-frequency clock waveforms for bitserial hardware. Triggered by a master clock input, the circuit outputs a fixed number of pulses followed by a completion signal. The design uses two coupled ring oscillators to produce dif...

A low-power sensor interface IC suitable for a differential frequency measurement application is demonstrated. The circuit is used in a FBAR sensor system which includes a sensor and a reference FBAR. The sensor signal is processed and a digital output representing the sensor input is transmitted using a two wire serial interface. The architecture is entirely digital and benefits from scaling t...

Home and industrial appliances do usually have RS232 ports to enable computer control. In this paper we present a module to both extend the serial communications port for other devices or protocol adapters and to allow remote control by SMS messaging. To do so, the module must include a port arbiter to handle bi-directional communications between a RS232 and the two other ports (RS232 and GSM).

This paper provides an estimation model for calibrating the kinematics of manipulators with a parallel geometrical structure. Parameter estimation for serial link manipulators is well developed, but fail for most structures with parallel actuators, since the forward kinematics is usually not analytically available for these. We extend parameter estimation to such parallel structures by developi...

Using good properties of an optimal normal basis of type I in a finite field F2m , we present a design of a bit serial multiplier of Berlekamp type, which is very effective in computing xy. It is shown that our multiplier does not need a basis conversion process and a squaring operation is a simple permutation in our basis. Therefore our multiplier provides a fast and an efficient hardware arch...

ABSTRACT This paper introduces a digit-serial GF(2m) multiplier for use in the polynomial basis. The multiplier works with the most significant digit first and is scalable to an arbitrary digit size and can be constructed for any GF(2m). It is derived from a commonly used MSB first bit-serial multiplier, known as the standard shift-register multiplier. As the latency of the multiplier decreases...

The high level of accumulated expertise by ULIS and CEA/LETI on uncooled microbolometers made from amorphous silicon layer enables ULIS to develop 384 x 288 (1⁄4 VGA) IRFPA formats with 25 μm pixel-pitch designed for high end applications. This detector ROIC design relies on the same architecture as the full TV format ROIC one (detector configuration by serial link, user defined amplifier gain,...

In this paper a new dynamic differential logic style is presented. A non-precharged single phase clocking scheme is used. The logic is suitable for high speed and low power operation in both bit-serial and bit-parallel implementations, since all logic nets are purely in NMOS and merged with the latches. The logic style is also robust for clock slope and yield a data noise margin equal to Vdd/2.

In this paper, we describe the design and implementation of OTCA (Ownership-Tagged Cell Allocation) M C protocol for a unidirectional slotted ring network with a distributed fair medium access. A point-topoint @2p) interconnection network in a ring topologv with a high-speed serial link and the sharing of network bandwidth among multiple communicating nodes offers a very promising low cost solu...