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Fast and accurate estimation of soft error rate in VLSI circuits is an essential step in a soft error tolerant ASIC design. In order to have a cost e®ective protection against radiation e®ects in combinational logics, an accurate and fast method for identi ̄cation of most susceptive gates and paths is needed. In this paper, an e±cient, fast and accurate method for soft error propagation probabil...

uture wireless multimedia terminals will have a variety of applications that require speech recognition capabilities. In this paper, we consider a robust distributed speech recognition system where representative parameters of the speech signal are extracted at the wireless terminal and transmitted to a centralized automatic speech recognition (ASR) server. We propose several unequal error prot...

Smaller feature size, higher clock frequency and lower power consumption are of core concerns of today’s nano-technology, which has been resulted by continuous downscaling of CMOS technologies. The resultant ‘device shrinking’ reduces the soft error tolerance of the VLSI circuits, as very little energy is needed to change their states. Safety critical systems are very sensitive to soft errors. ...

We analyze the soft error tolerance of a latch in 65-nm SOTB (Silicon on Thin BOX) and 28-nm UTBB (Ultra Thin Body and BOX) processes by a PHITS-TCAD simulation system. The proposed system is composed of two parts, the device-simulation and the physics simulation by PHITS (Particle and Heavy Ion Transport code System). The alpha and neutron induced soft error rate can be analyzed without test c...