In Computed Tomography (CT), two-dimensional (2-D) slices or three-dimensional (3-D) volumes of an object are reconstructed from many projected line-integrals (usually x-ray transmission data) around the object. As the data collection capabilities and reconstruction algorithms for CT have become more sophisticated over the years, the demands on computer systems have become correspondingly great...

In this brief an approach is proposed to achieve energy savings from reduced voltage operation. The solution detects timing-errors by integrating Algorithm Based Fault Tolerance (ABFT) into a digital architecture. has been studied with systolic array matrix multiplier operating at voltages, detecting errors on-the-fly avoid demanding memory round-trips. analysis of the done using analog-digital...

This paper proposes a two-dimensional (2-D) VLSI architecture using a uni ed systolic array for fast computation of the discrete cosine transform/discrete sine transform/discrete Hartley transform (DCT/DST/DHT). The N -point discrete transform is decomposed into evenand oddnumbered frequency samples and they are computed independently at the same time. The proposed uni ed systolic array archite...

Indexing terms: Maximum driving, Systolic array ABSTRACT In this work, we develop an optimized binary tree-level rule for the design of systolic array structure of Delay LMS (DLMS) adaptive filter Using our developed method higher convergence rate can be obtained without sacriJictng the properties of systolic array structure. Also, based on our optimized tree rule, user can easily design any ev...

In this paper, we introduce the Systolic Recon gurable Mesh (SRM), which combines aspects of the recon gurable mesh with that of systolic arrays. Every processor controls a local switch that can be recon gured during every clock cycle in order to control the physical connections between its four bi-directional bus lines. Data is input on one side of the systolic recon gurable mesh and output fr...