In this paper we describe an efficient implementation of an IEEE 754 single precision floating point multiplier targeted for Xilinx Virtex-5 FPGA. VHDL is used to implement a technology-independent pipelined design. The multiplier implementation handles the overflow and underflow cases. Rounding is not implemented to give more precision when using the multiplier in a Multiply and Accumulate (MA...

Multiplier is an important key element used for arithmetic operations in digital signal processor. Power consumption in multiplier is more when compared with adders and subtractors. So reducing the power consumption of multiplier makes a digital signal processor more efficient. A Wallace tree multiplier is an efficient high speed multiplier that multiplies two integers. Here a 4*4 Wallace tree ...

High-speed parallel multipliers are one of the keys in RISCs (Reduced Instruction Set Computers), DSPs (Digital Signal Processors), and graphics accelerators and so on. Array multiplier, Booth Multiplier and Wallace Tree multipliers are some of the standard approaches used in implementation of binary multiplier which are suitable for VLSI implementation. A simple digital multiplier (henceforth ...

This paper presents low power 8x8 bit multipliers which are implemented with Tanner Tool v13.0 at 500MHz frequency with 65nm technology which is having a supply voltage 1.0v. There are different CMOS multiplier circuits are analyzed names as Braun multiplier, Wallace tree multiplier, Row bypass Braun multiplier, Column bypass Braun multiplier, Row and Column bypass Braun multiplier and these mu...

generalizing the concepts of -fuzzy (left, right, lateral) ideals, -fuzzy quasi-ideals and   -fuzzy bi (generalized bi-) ideals in ternary semigroups, the notions of -fuzzy (left, right, lateral) ideals, -fuzzy quasi-ideals and -fuzzy bi (generalized bi-) in ternary semigroups are introduced and several related properties are investigated. some new results are obtained.

The blocks of a balanced ternary design, BTD(V,B; ρ1, ρ2, R;K,Λ), can be partitioned into two sets: the b1 blocks that each contain no repeated elements, and the b2 = B − b1 blocks containing repeated elements. In this note, we address, and answer in some particular cases, the following question. For which partitions of the integer B as b1 + b2 does there exist a BTD(V,B; ρ1, ρ2, R;K,Λ)?

Let (ωn)0<n be the sequence known as Integer Sequence A047749 In this paper, we show that the integer ωn enumerates various kinds of symmetric structures of order two. We first consider ternary trees having a reflexive symmetry and we relate all symmetric combinatorial objects by means of bijection. We then generalize the symmetric structures and correspondences to an infinite family of symmetr...

The Wallace Multiplier is mainly used in the Arithmetic & Logic Unit (ALU) to perform the scientific computation in processors, controller etc... The existing multiplication technique like booth multiplier, array multiplier etc requires more time in multiplications. Hence Wallace Multiplier has been designed by using the parallel process to reduce the delay. The regular Wallace Multiplier requi...

A new realization of non-recursive digital filters using operation on ternary delta modulated signal is proposed. Direct operation on ternary delta modulated signal will be derived mathematically and a hardware implementation of ternary arithmetic operation will be shown. The primary advantage of the ternary scheme is the simplicity of the hardware and reduction in connections and interconnecti...

In this paper a low power and low area array multiplier with carry save adder is proposed. The proposed adder eliminates the final addition stage of the multiplier than the conventional parallel array multiplier. The conventional and proposed multiplier both are synthesized with 16-T full adder. Among Transmission Gate, Transmission Function Adder, 14-T, 16-T full adder shows energy efficiency....