There has been some recent interest in the subject of whether circuits should be tested with built-in self-test (BIST) or automated test equipment (ATE). As with many such debates, neither extreme is a viable position, and the true answer lies somewhere in the middle. BIST patterns have their place with scan patterns, IDDQ patterns, etc. as part of a test program driven by ATE. 1. " Putting a t...

Multi-port memories are widely used as embedded cores in all communication System-on-Chip devices. Due to their high complexity and very low accessibility, Built-In Self-Test (BIST) is the most common solution implemented to test the different memories embedded in the system. This paper presents a programmable BIST architecture, based on a single microprogrammable BIST Processor and a set of me...

A new technique for diagnosis in a scan-based BIST environment is presented. It allows non-adaptive identification of both the scan cells that capture errors (space information) as well as a subset of the failing test vectors (time information). Having both space and time information allows a faster and more precise diagnosis. Previous techniques for identifying the failing test vectors during ...

This paper reported extensive study and research proposal of Post simulation and behavioral modeling of Second Order sigma-delta modulator BIST technique in which include non-ideality factor such as offset error and clock jitters. For the test of the digital parts, BIST techniques have been developed and are broadly implemented in current chips. BIST technique not only avoids depending on the o...

The high integration level, complexity and performance achieved in new nanometer technologies make IC (Integrated Circuits) products very difficult to test. Moreover, long-term operation brings aging cumulative degradations, and new processes and materials lead to emerging defect phenomena. The consequence is obtaining products with increased variability in their behavior, more susceptible to d...

In this paper we propose a novel built-in self-test (BIST) design for embedded SRAM cores. Our contribution includes a compact and efficient BIST circuit with diagnosis support and an automatic diagnostic system. The diagnosis module of our BIST circuit can capture the error syndromes as well as fault locations for the purposes of repair and fault/failure analysis. In addition, our design provi...

This paper proposes a static test approach suitable for built-in-self-test (BIST) of Analog-to-digital converter Intellectual Property (IP). Static parameters (INL, DNL, gain, offset) are tested without using test equipment. The proposed BIST structure is applicable for testing models of analog-to-digital converters up to 12bits of resolution. Comparison results with dynamic test equipment vali...

In this paper, a new algorithm and a new BIST structure for efficiently testing dual port memories that is used widely as embedded memory, is proposed. The proposed test algorithm is able to detect the dual port memories faults and has shorter test time and the test patterns in comparison to existing test algorithms. In addition, the presented BIST has efficient structure that requires lesser h...

Built-in self-test techniques have been widely researched and adopted for reasons of improvements in test time and test cost, reduction in test resources required for test of large chips with embedded cores, and for field testability. While the adoption of these techniques is becoming prevalent, there continue to be challenges in making BIST solutions comprehensive to meet several design and ap...

The technological development is enabling the production of increasingly complex electronic systems. All such systems must be verified and tested to guarantee their correct behavior. As the complexity grows, testing has become one of the most significant factors that contribute to the total development cost. In recent years, we have also witnessed the inadequacy of the established testing metho...