In this paper, we present a verification methodology that integrates formal verification techniques with verification by simulation, thereby providing means for generating simulation test suites that ensure coverage. We derive the test suites by means of BDD-based symbolic techniques for describing and traversing the implementation state space. In our approach, we provide a high-level of contro...

This paper introduces a specific architecture including an infrastructural IP for functional verification and diagnostics, which is suitable for functional core-based testing of an MPEG4 SoC. Our advanced MPEG4 SoC results in a high complexity SoC with limited physical access to many different functional cores. The proposed test method provides direct monitoring and control for each core, which...

ABSTRACT:This paper applied UVM (Universal Verification Methodology), an advanced verification methodology which was based on SystemVerilog language to build AES (Advanced Encryption Standard) IP verification platform and environment. Functional verification of the AES module, through a large number of testcases and constrained random test could achieve 100% functional coverage. In addition, th...

80 0740-7475/04/$20.00 © 2004 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers TO COMPETE IN THE MARKETPLACE, all semiconductor products have tight time-to-market requirements. With design complexity exploding, functional verification is now on the critical path to RTL signoff and relies mainly on extensive vector simulation. A typical microprocessor requires bi...

In the classic approach to logic model checking, software verification requires a manually constructed artifact (the model) to be written in the language that is accepted by the model checker. The construction of such a model typically requires good knowledge of both the application being verified and of the capabilities of the model checker that is used for the verification. Inadequate knowled...

Background: The dynamic phantom is one of the best tools to study the impact of motion on tumor target delineation and absorbed dose verification during dose delivery. Materials and Methods: this study, a 6-DOF (degrees of freedom) phantom was designed following the stacked serial kinematics and assembled by six commercial motion stages to generate 6-DOF motion, which were RotX (pitch, around X...

Assertion-Based Verification (ABV) aims at guaranteeing that designs obey properties, usually expressed under the form of logic and temporal formulae. In dynamic ABV, those properties are checked at runtime (e.g., during simulation). In the context of simulation-based verification, the significance of the selected test sequences is well known. Moreover, if the validity of properties is also to ...

In this paper we describe a method of automated test program generation intended for systematic functional verification of microprocessors. The method supplements such widely-spread practical approaches as software-based verification and random generation. In our method, construction of test programs is based on microprocessor model, which includes structural model and instruction set model. Th...

In this survey, we prove that the Universal Verification Methodology, UVM, is not only efficient in verifying large-gate-count IP-based System-on-Chip designs, but it is also efficient in verifying small designs, in comparison with the conventional verification techniques, specifically VHDL testbenches. We have built both a UVM verification environment and a VHDL test-bench to verify the operat...