734 The JPEG standard is most widely used method of lossy compression for digital photography. In this paper, we will discuss the implementation of JPEG Encoder for FPGAs. The target device is a Stratix IV FPGA. The JPEG Encoder was synthesized and simulated using the Quartus FPGA design software at the clock frequency of 122.5 MHz. The design was tested on an image for different values of the ...

This paper describes the architecture of a time-multiplexed FPGA. Eight configurations of the FPGA are stored in onchip memory. This inactive on-chip memory is distributed around the chip, and accessible so that the entire configuration of the FPGA can be changed in a single cycle of the memory. The entire configuration of the FPGA can be loaded from this on-chip memory in 3011s. Inactive memor...

This work deals with DPA-resistant logic styles, i.e., celllevel countermeasures against power analysis attacks that are known as a serious threat to cryptographic devices. Early propagation and imbalanced routings are amongst the well-known issues of such countermeasures, that – if not considered during the design process – can cause the underlying cryptographic device to be vulnerable to cert...

This thesis presents a comprehensive test generation framework for FPGA logic elements and interconnects. It is based on and extends the current state-of-the-art. The purpose of FPGA testing in this work is to achieve reliable reconfiguration for a FPGA-based runtime reconfigurable system. A pre-configuration test is performed on a portion of the FPGA before it is reconfigured as part of the sy...

This paper presents an overview about FPGA based fault injection tools which are developed by using the instrumentation technique or modification in the original code. The fault injection technique is used to evaluate dependability parameters of computer based embedded systems or safety critical systems, by injecting faults in a system. An observation on the behaviour or of the response for bot...

In this paper, an Infinite Impulse Response (IIR) filter has been designed and simulated on an Field Programmable Gate Arrays (FPGA). The implementation is based on Multiply Add and Accumulate (MAC) algorithm which uses multiply operations for design implementation. Parallel Pipelined structure is used to implement the proposed IIR Filter taking optimal advantage of the look up table of target ...

Simulation is the most viable solution for the functional verification of SoC. The acceleration of simulation with multi-FPGA is a promising method to comply with the increasing complexity and large gate capacity of SoC. The most time-consuming factor of multi-FPGA simulation accelerator is synchronization time between simulator and multi-FPGA system. Time-multiplexing of interconnection wires ...

The steadily growing performance of processors for embedded systems make the usage of the platform independent Java system more and more attractive. However, the usual techniques known for acceleration of the Java Virtual Machine, widely used on desktop computers, don’t apply well in general to this class of devices, the most prominent example is the Just-in-Time-Compilation (JIT). This is caus...

With CMOS technology aggressively scaling towards the 22-nm node, modern FPGA devices face tremendous aging-induced reliability challenges due to bias temperature instability (BTI) and hot carrier injection (HCI). This paper presents a novel anti-aging technique at the logic level that is both scalable and applicable for VLSI digital circuits implemented with FPGA devices. The key idea is to pr...

The Theoretical Development of a New High Speed Solution for Monte Carlo Radiation Transport Computations. (December 2005) Alexander Samuel Pasciak, B.S., University of Washington Chair of Advisory Committee: Dr. John R. Ford Advancements in parallel and cluster computing have made many complex Monte Carlo simulations possible in the past several years. Unfortunately, cluster computers are larg...