This Paper proposes the implementation of multiplier using ancient Indian vedic mathematics (Urdhvatiryagbhyam) that has been modified to improve performance of high speed mathematics, it shows the modified architecture for a 16*16 Vedic multiplier module using Urdhvatiryagbhyam technique. The design implementation is described in both at gate level and high level RTL code using Verilog Hardwar...

The Vedas are the first texts in the library of mankind. They are universally acknowledged to be the most precious Indian Heritage. The antiquity to the Vedic civilization is debated to a great extent but indeed there is no civilization known to humanity with such antiquity as Vedic Aryan Civilization. The so-called Aryans would have originated in the Aryavarta. N. J. Lockyer has declared: šThe...

High speed Arithmetic Units (AUs) are widely used in architectures used in signal and image processing applications. AUs involve multifunctions and have multiplier as the critical element. In this paper, we present design and implementation of high speed and area efficient AU using Vedic algorithm. The work uses a simple “vertical and crosswise sutra” of Vedic mathematics to produce low complex...

This note is about some of the technical work that UCL CS people have done, partly Jon at HP during the first quarter of 1998, but also previous work using NS under several projects, notably MERCI, HIPAPRCH and DARPA work. The work described is a series of seperate efforts to add protocols to NS, and then a design effort to enhance NS to provide interworking between real and simulated (actual a...