As embedded systems are becoming increasingly complex, the design process and verification have become very time-consuming. Additionally, specifying hardware manually in a low-level hardware description language like VHDL is usually an error-prone task. In our group, a tool (the CλaSH compiler) was developed to generate fully synthesisable VHDL code from a specification given in the functional ...

The underlying nature of adiabatic circuits is most accurately characterized at the circuit level as it for traditional technologies. In order to scale system designs logic technologies, modeling necessary. Logic models can facilitate design, development, and verification large digital systems that may be infeasible using simulators. Adiabatic powered with a four stage power clock consisting id...

UT Mixed-Signal Simulator is a mixed-signal, mixeddomain, and mixed-language design environment which supports VHDL-AMS 1999, VHDL-2002, Verilog 2001, SystemVerilog 2005 assertions, and SystemC 2005.

This paper provides an overview of the VHDL AMS hardware description language for analog and mixedsignal applications like the switched mode power supply which is designed by describing the major elements or components of the system with the help of this hardware descriptive language and illustrating it using Hamster which is a simulation software for VHDL and Verilog Descriptive Language. Inde...

This paper will describe aspects relating the modelling of a mixed-signal system with the aim to describe the system in a single language prior to any detailed implementation strategy. With reference to a communications system modelling case study, VHDL-AMS, an extension to the industry standard VHDL Hardware Description Language (HDL) for digital circuits and systems, will be used. Recently, t...

HML (Hardware ML) is an innovative hardware description language based on the functional programming language SML (Standard ML). HML is a high-order language that supports polymorphic functions. HML's advanced type system provides many constructs that are important to hardware descriptions but are lacking in the more mature, widely used hardware description languages such as VHDL and Verilog. I...

The aim of this paper is to present an approach that allows the generation of VHDL from system level speci cations in SDL. Our approach overcome the main known problem encountered by previous work which is the communication between di erent processes. We allow SDL communication to be translated into VHDL for synthesis. This is made possible by the use of an intermediate form that support a powe...

by Mark Dean Mueller With the increasing use of mixed signal analog and digital technologies in circuit design, there becomes a growing need for a method to simulate such circuits quickly, easily and accurately. Modeling the components structurally with an analog simulation tool is a common technique. A more powerful method would be to behaviorally model both types of components at a higher lev...

Dedicated hardware can be used when images and video are acquired and processed. In this paper, a histogram equalization algorithm is written in a Hardware Description Language for future implementation in reconfigurable hardware. The goal of this project is to implement a histogram equalization algorithm using VHDL for a real-time processing system on a Field Programmable Gate Array (FPGA). Th...