While multi-processor system-on-chips (MPSOCs) with network-on-chip (NOC) interconnect are becoming increasingly common to meet the constant performance demand, it is due to communication delays in the NOC extremely complicated to ensure that software executes correctly. In this paper, we extend our architecture that non-intrusively observes global properties at run time using distributed monit...

Network-on-Chip (NoC) as a promising design approach for on-chip interconnect fabrics could overcome the energy as well as synchronization challenges of the conventional interconnects in the gigascale System-on-Chips (SoC). The advantages of communication performance of traditional wired NoC will no longer be continued by the future technology scaling. Packets that travel between distant nodes ...

The goal of this end of term work is to evaluate the impact of the Network-on-Chip (NoC) parameters over the performance of applications on Multiprocessors Systems-on-Chip (MPSoCs). Nowadays, MPSoCs have so many constraints of performance that bus-based communications are not able to achieve the full potential of MPSoCs. Therefore, the adoption of networks-on-chip (NoCs) is a trend for the comm...

Journal of Electronic Systems Volume 6 Number 2 June 2016 ABSTRACT: The power dissolute by the links of a network-on-chip (NoC) starts to play with the power dissipated by the additional basic elements of to the communication sub-system within specifically, the routers &network interfaces (NIs). In this, we present a conventionaldata encoding schemes meant to reducing the dissipated of power by...

With the progress of deep submicron technology power consumption and temperature related issues have become two of the most critical aspects for chip design. Therefore, very large-scale integrated systems like Systems-on-Chip (SoCs) are exposed to an ever increasing thermal stress. This necessitates effective mechanisms for thermal management. In this paper we propose to precompute and proactiv...

Optical network-on-chip (ONoC) has been proposed to provide higher bandwidth and lower power consumption for future multicore systems. However, due to the intrinsic characteristic of optical devices, crosstalk noise is a potential issue for ONoC. The traditional routing algorithms for Benes ONoC have not considered the aspect of crosstalk. In this paper, we build the crosstalk model of the opti...

The Network on Chip (NoC) paradigm is rapidly replacing bus based System on Chip (SoC) designs due to their inherent disadvantages such as non-scalability, saturation and congestion. Currently very few tools are available for the simulation and evaluation of on-chip architectures. This study proposes a generic object oriented model for performance evaluation of on-chip interconnect architecture...

Networks-on-Chip (NoCs) aim at meeting the communication scalability required by Systems-on-Chip (SoCs), which are computing systems integrated into a single chip. As well as traditional distributed systems, a SoC and its network are susceptible to attacks to their security properties. This paper presents a survey that was conducted in order to identify the techniques that have been applied to ...

The Network-on-Chip (NoC) paradigm has been herald as the solution to the communication limitation that System-On-Chip (SoC) poses. However, power Consumption is one of its major defects. To ensure that a high performance architecture is constructed, analyzing how power can be reduced in each area of the network is essential. Power dissipation can be reduced by adjustments to the routers, the a...

The wavelength routed optical network (WRON) [1] is a promising optical interconnection architecture that can be integrated into a System-on-Chip (SoC) to replace traditional wire-connected on-chip micro-networks which pose severe bandwidth limitations on future super large SoC chips. In this paper, we present the architecture of WRON and generalize the routing schemes based on source address, ...