In this paper we present HARE, a new hierarchical approach to register allocation and assignment for multiple issue load/store architectures. HARE makes extensive use of execution estimates and functional unit availability information to select values for spilling and to place the spill code in locations that minimize the increase in the overall execution time of the program. Incorporated in HA...

This paper sketches the design and implementation of DeviceDriver Analyzer for x86 (DDA/x86), a prototype analysis tool for finding bugs in stripped Windows device-driver executables (i.e., when neither source code nor symbol-table/debugging information is available), and presents a case study. DDA/x86 was able to find known bugs (previously discovered by source-code-based analysis tools) along...

This paper describes our experience in porting Compaq’s Fast VM from the Alpha processor architecture to the Intel x86 processor architecture. We encountered several opportunities and pitfalls along the way in porting a JVM designed for a RISC architecture to a CISC architecture. Our goal was to preserve most of the FastVM’s performance benefits already available on the Alpha platform, and modi...

The establishment of trust relationships to a trusted platform relies on the process of validation. Validation allows an external entity to build trust in the expected behaviour of the platform based on provided evidence of the platform’s configuration. In a validation mechanism such as remote attestation, the trusted platform exhibits verification data created during a start up process. These ...

Real multiprocessors do not provide the sequentially consistent memory that is assumed by most work on semantics and verification. Instead, they have relaxed memory models, typically described in ambiguous prose, which lead to widespread confusion. These are prime targets for mechanized formalization. In previous work we produced a rigorous x86-CC model, formalizing the Intel and AMD architectu...