The COordinate Rotation DIgital Computer (CORDIC) algorithm is an arithmetic algorithm to evaluate various elementary functions through a series of iterative operations. In this paper, a high-speed sine/cosine generator is based on double rotation of the original CORDIC algorithm by predicting all the rotation directions from the initial input angle. The proposed architecture has a simple predi...

In the era of the Internet of Things, smart electronic devices facilitate processes in our everyday lives. Texas Instrument's MSP430 microcontrollers target low-power applications, among which are wireless sensor, metering and medical applications. Those domains have in common that sensitive data is processed, which calls for strong security primitives to be implemented on those devices. Curve2...

This paper describes a user-level instruction set for a 32-bit processor. The machine is simple, compact, and well suited to the C language. In fact, even for 16-bit applications it is reasonable to expect the instruction space for C programs to be 10 to 15 % smaller than for the PDP-11. Most of the desirable properties of this instruction set are the direct result of the design methodology: 1....

Digital multipliers are among the most critical arithmetic functional units. The overall performance of these systems depends on the throughput of the multiplier. Meanwhile, the negative bias temperature instability effect occurs when a pMOS transistor is under negative bias (Vgs= −Vdd), increasing the threshold voltage of the pMOS transistor, and reducing multiplier speed. A similar phenomenon...

In a signal processing like application, the performance of the whole processing is a function of how fast the FFT operation is done .The speed of the operation is directly dependent on efficiency of the multiplier in the design. The paper discusses about a multiplier implementation where the speed of computation is improved by using twin-precision scheme and row decomposition schemes. To lower...

Stack-based attacks typically require that attackers have a good understanding of the stack layout of the victim program. In this paper, we leverage specific features on ARM architecture and propose a practical technique that introduces randomness to the stack layout when an Android application executes. We employ minimal binary rewriting on the Android app that produces randomized executable o...

The content of this paper is intended to highlight the performance of the 32-bit LEON 3FT processor in terms of execution speed in comparison with the currently used 16-bit processor. Therefore, the work related to this paper is considered to be an upgrade over the previous implementation. The proposal for such an enhancement has been materialized successfully by means of a LEON 3FT processor b...

In this paper, an efficient code size optimization instruction set architecture targeting embedded telecommunication applications is introduced. Nowadays, mixed 16-bit and 32bit size instruction set approaches are commonly used to achieve code size reduction while minimizing performance loss. They are usually designed with some restrictions such as reducing the number of accessible registers, m...

In this work one bit Full Adder with Ten transistors have been proposed. Reducing Power dissipation, supply voltage, leakage currents, area of chip are the most important parameters in today`s VLSI designs. The system reliability can be increased by reducing the cost, weight and physical size and it is achieved by decreasing the transistor count. Therefore the minimum power consumption target a...