In this work, we present a 200 MHz to 1.6 GHz digital delay-locked loop (DLL) for per-pin deskew applications. The proposed phase shifters apply linear and scalable circuit architecture for the pin-to-pin delay mismatch of parallel I/O pins. The proposed phase detector with a detection window and the proposed consecutive phase decision method reduce the sensitivity to reference clock jitter. A ...

Abstract This paper studies the commissioning method of phase-locked loops to enable phasemeters achieve required frequency and phase accuracy. The influence different phasemeter structures on performance is explored. Through theoretical analysis experiments, debugging process loop clarified, which can meet its basic indexes, especially accuracy, optimized for traditional structure.

Homodyne optical phase-locked loop (OPLL) is one kind of PLLs applied in field to achieve phase locking between two signals. Although there are already some software emulation and s-domain modeling methods studied for homodyne OPLL, few studies about z-domain model OPLL reported. For digital OPLL(DOPLL), the performance DOPLL can be analyzed more accurately by model. So a methodology proposed l...

flip-flop circuit technique has been designed. CMOS new flip-flop circuit with CMOS domino logic which, All the flip-flops were designed using UMC 180. Recognize standard circuit symbols for D Type flip-flops. though can be largely prevented by using the Edge Triggered D Type flipflop illustrated in Fig 5.3.3. locked loop, using 32 nm CMOS technology. Here we design D flipflop for Phase locked ...

An approach to the derivation of variable loop gain sequences of dual-loop digital phase-locked loop (DPLL) [1] is developed based on some modifications of the Kalman filtering formulation. It is shown that optimal loop gain sequences which are independent of measurement noise statistics can be obtained under a deterministic source model. Computer simulation results demonstrate that the adaptiv...

The most versatile application for digital phase locked loops is for clock generation and clock recovery in any complex computer architecture like a microprocessor or microcontroller, network processors. Digital Phase locked loops are commonly used to generate timing on chip clocks in high performance mixed signal analog and digital systems. Most of the systems employ digital PLL mainly for syn...