In this paper, we analyze the effect of clock jitter on the performance of OFDM-based systems applying digital IF architecture. A bandpass Σ∆ ADC is used for the analog to digital conversion process. An accurate and realistic model of the clock jitter in bandpass Σ∆ ADC is implemented. Results from this paper show that clock jitter severely degrades OFDM system performance by introducing both p...

In recent years, there has been an explosive demand for wireless and portable applications, which resulted in more flexible communication systems that can handle various standards in different environments. In an ideal software radio, the data conversion occurs immediately after the signal received from the receiving antenna.. This paper presents multi-standard reconfigurable modulators, which ...

Pixel level processing promises many significant advantages including high SNR, low power, and the ability to adapt image capture and processing to different environments by processing signals during integration. However, the severe limitation on pixel size has precluded its mainstream use. In this paper we argue that CMOS technology scaling will make pixel level processing increasingly popular...

In this paper, a 10-bit 0.5V 100 kS/s successive approximation register (SAR) analog-to-digital converter (ADC) with a new fully dynamic rail-to-rail comparator is presented. The proposed comparator enhances the input signal range to the rail-to-rail mode, and hence, improves the signal-to-noise ratio (SNR) of the ADC in low supply voltages. The e®ect of the latch o®set voltage is reduced by pr...

Analog-to-digital converters (ADCs) are essential building blocks in many electronic systems which require digital signal processing and storage of analog signals. Traditionally, ADCs are considered a power hungry circuit. This thesis investigates ADC design techniques to achieve high-performance with low power consumption. Two designs are demonst rated. The first design is a voltage scalable z...

A charge-based flash analog digital converter (ADC) circuit architecture is presented, which can be used in various artificial neural network (ANN) applications where compactness and high conversion speed are critical. The 4-bit $'& KDV EHHQ UHDOL]HG ZLWK P GRXEOH SRO\ SURFHVV DQG tested, confirming its linearity over the full range and a conversion speed of 10 Msamples / s. Introduction : The ...

Resistive sensors configured as Wheatstone bridges are primarily used to sense pressure, temperature or loads. An external A/D converter (ADC) and a digitally Programmable Gain Amplifier (PGA) can easily be used to convert the difference voltage from these resistor bridge sensors to usable digital words for manipulation by the microcontroller. When the PGA is used in this system, the other chan...

Analog-to-digital converters (ADCs) are key design blocks in modern microelectronic digital communication systems. An analog?to?digital converter (ADC) acts as a bridge between the analog and digital worlds. It is a necessary component whenever data from the analog domain, through sensors or transducers, should be digitally processed or when transmitting data between chips through either long-r...

The “Split ADC” architecture enables fully digital calibration and correction of nonlinearity errors due to capacitor mismatch in a Successive Approximation (SAR) ADC. The die area of a single ADC design is split into two independent halves, each converting the same input signal. Total area and power is unchanged, resulting in minimal increase in analog complexity. For each conversion, the half...

A 3-bit ADC for X-band applications that can work at a sampling rate of 11 GS/s is presented in this paper. Current comparators are used to achieve the high sampling rate of 11 GHz at X-band. A 3-bit current-steering DAC is also designed for testing the high-speed ADC. The ADC-DAC RFIC is implemented in a 0.12 μm SiGe technology and occupies a core area of 1.0 x 0.8 mm. The ADC can operate with...