This paper describes an ASIC yield model based on the CMOS bridge fault model. The model predicts defect sensitive area early in the design cycle as a function of number of gates and nets.

This paper describes VALID, a platform for testing student designed ASICs and for teaching the basics of FPGA design. VALID is designed to maximize ease of use from a student’s perspective while maintaining enough flexibility for its use as an FPGA development and instruction platform. This system was designed entirely by students, has been successfully manufactured and is currently being used ...

This paper addresses the design of reactive real-time embedded systems. Such systems are often heterogeneous in implementation technologies and design styles, for example by combining hardware ASICs with embedded software. The concurrent design process for such embedded systems involves solving the specification, validation, and synthesis problems. We review the variety of approaches to these p...

We show that a direct transposition of a generic IC architecture on a QCA technology is rendered inefficient by characteristics intrinsic to the model. This analysis constitutes the motivation for an application-specific architectural approach based on regular blocks proposed further in the paper. The basic architectural model is specified and a design methodology allowing the mapping of regula...

The recent discovery of the constructive use of pairings in cryptography has opened up a wealth of new research options into identitybased encryption. In this paper, we will investigate the possible use of pairings in constrained environments. The focus will be on an small, energy efficient ASIC implementation of an accelerator for the Tate pairing over a supersingular curve. The results are en...

Project: BANDIT ESPRIT 29260 Doc. Title: Intermediate design case report about noise coupling analysis and reduction methodology.

Abstract--We have proposed, in this paper a, TCAD/DA methodology for MPU and ASIC with updated processes and devises, which allow a predictive chip-design with quick quantitative correlation studies between process-recipe and CKT & delay parameters required in DA works. Effects of statistical process variation on 0.35um CMOS have been rigorously characterized with a new global TCAD calibration ...

Over the last decade the successful design and fabrication of complex MEMS (MicroElectroMechanical Systems), optical circuits and ASICs have been demonstrated. Packaging and integration processes have lagged behind MEMS research but are rapidly maturing. As packaging processes evolve, a new challenge presents itself, microsystem product development. Product development entails the maturation of...

At the current stratospheric value of Bitcoin, miners with access to significant computational horsepower are literally printing money. For example, the first operator of a USD $1,500 custom ASIC mining platform claims to have recouped his investment in less than three weeks in early February 2013, and the value of a bitcoin has more than tripled since then. Not surprisingly, cybercriminals hav...