Source-drain follower has been designed and implemented for monolithically integrated biosensor array. The circuit acts as a voltage follower, in which a sensing transistor is operated at fixed gatesource and gate-drain voltages. It operates at 10 nW power dissipation. The wide-swing cascode configurations are investigated in constant and non-constant biasing methods. The constant biased cascod...

A new 2xVDD-tolerant mixed-voltage I/O buffer circuit, realized with only 1xVDD devices in deep-submicron CMOS technology, to prevent transistors against gate-oxide reliability and hot-carrier degradation is proposed. The new proposed 2xVDD-tolerant I/O buffer has been designed and fabricated in a 0.13-lm CMOS process with only 1.2-V devices to serve a 2.5-V/1.2-V mixed-voltage interface, witho...

A very simple circuit design of a bidirectional input/output(I/O) buffer is proposed for mixed voltage interface applications. By a floating N-well circuit technique two series PMOS transistors are used as an active pull-up driver. Such a structure provides a simple circuit that requires only a single terminal pad, a single power supply, and is free of DC leakage current. Mixed voltage interfac...

A systematic method is introduced to the computational synthesis of CMOS voltage followers (VFs). The method is divided in three steps: generation of the small-signal circuitry by selection of nullators to model the behavior of a VF, and addition of norators to form nullatornorator joined-pairs; generation of the bias circuitry by addition of ideal biases according to the properties of nullator...

The optimistic analytical results for performance analysis of buffered banyan networks are mainly due to certain independence assumptions used for simplifying analysis. To capture more effects of cell correlation, a refined analytical model for both single-buffered and multiple buffered banyan networks is proposed in this paper. When cell output contention occurs at a 2 × 2 switch element, two ...

Background and Objectives: In this paper, a new design strategy was proposed in order to enhance bandwidth and efficiency of power amplifier. Methods: To realize the introduced design strategy, a power amplifier was designed using TSMC CMOS 0.18um technology for operating in the Ka band, i.e. the frequency range of 26.5-40GHz. To design the power amplifier, first a power divider (PD) with a ver...

We present a 1 2 all-optical packet switch. All the processing of the header information is carried out in the optical domain. The optical headers are recognized by employing the two-pulse correlation principle in a semiconductor laser amplifier in loop optical mirror (SLALOM) configuration. The processed header information is stored in an optical flip-flop memory that is based on a symmetric c...

We present a signal processing system with virtual instrumentation of a MEMS sensor to detect magnetic flux density for biomedical applications. This system consists of a magnetic field sensor, electronic components implemented on a printed circuit board (PCB), a data acquisition (DAQ) card, and a virtual instrument. It allows the development of a semi-portable prototype with the capacity to fi...

An optoelectronic integrated circuit (OEIC) receiver is realized with standard 0.25-μm SiGe BiCMOS technology for 850-nm optical interconnect applications. The OEIC receiver consists of a Si avalanche photodetector, a transimpedance amplifier with a DC-balanced buffer, a tunable equalizer, and a limiting amplifier. The fabricated OEIC receiver successfully detects 12.5-Gb/s 2(31)-1 pseudorandom...

The design of a 50 0 impedance matched two-tofour level converter GaAs IC for two-electrode semiconductor optical amplifier (SOA) modulators is presented. The designed IC exhibits eye diagrams with eye openings of better than 0.30 V and a spacing between adjacent output signal levels of 0.33 V for output symbol rates of up to 2 Gsym.boVs corresponding to input bit rates of up to 4 Gb/s. A novel...