Design of high speed and low power data path logic systems are one of the most challenging areas of research in VLSI system design. Adder circuit is the main building block in DSP processor. However, Digital adders suffer with the problem of carry propagation delay. To alleviate this problem Carry Select Adder (CSLA) are used in computational unit. Carry Select Adder one of the fastest adder am...

Power dissipation is one of the most important design objectives in integrated circuits, after speed. As adders are the most widely used components in such circuits, design of efficient adder is of much concern for researchers.From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a fewer transistors to significant...

This paper presents a VLSI architecture for three-operand binary adder. The proposed design is based on carry-select adder (CSLA) and Han-Carlson (HCA) Carry-select known its high speed low power consumption. uses novel carry-in selection scheme that reduces the number of logic gates required carry generation. Additionally, (HCA), parallel prefix two-operand adder, can also be used addition, si...

Carry Select Adder (CSLA) which provides one of the fastest adding performance. Traditional CSLA require large area and more power. Recently a new CSLA adder has been proposed which performs fast addition, while maintaining low power consumption and less area. This work mainly focuses on implementing the 128 bit low power and area efficient carry select adder using 0.18 μm CMOS technology. Base...

According to the modern research the rapid development of portable electronics is forcing the designers to elevate the existing designs for better performance. Addition is the crucial arithmetic operation used in various applications like, Digital signal processors, ALUs, math processor and in various other scientific applications. In this paper, we proposed the 1-bit CSA with gates having diff...

We present a radix-4 static CMOS full adder circuit that reduces the propagation delay, PDP, and EDP in carry-based adders compared with using a standard radix-2 full adder solution. The improvements are obtained by employing carry look-ahead technique at the transistor level. Spice simulations using 45 nm CMOS technology parameters with a power supply voltage of 1.1 V indicate that the radix-4...

This paper presents novel architectures for fast binary addition which can be implemented using multi-plexers only. Binary addition is carried out using a fast redundant-to-binary converter. It is shown that appropriate encoding of the redundant digits and re-casting the binary addition as a redundant-to-binary conversion reduces the latency of addition from Wt fa to Wt mux where t fa and t mux...

Multiple constant multiplication scheme is the most effective common sub expression sharing technique which is used for implementing the transposed FIR filters. Ripple carry operation allows adder tree to minimize hardware cost, unfortunately it detriment timing and gives low speed operation. To outperform this high speed adder is proposed and analyzed for real time speech signal applications. ...