A 6-bit weighted-current-sink video digital-to-analog converter (DAC) with 10-90 percent rise/fall time of 4 ns, integrated with a double-metal 3pm CMOS technology, is described. Current-source matching, glitch reduction, and differential switch driving aspects are considered. A new circuit solution and a nonconventional layout technique yield a high conversion rate with a standard CMOS technol...

In mixed-signal designs, substrate coupling of digital circuit noise can severely compromise the behavior of sensitive analog circuits. Proper characterization of substrate noise is therefore indispensable. In this paper, we present an experimental setup for the characterization of directly coupled substrate noise in bulk-type CMOS. We have integrated configurable substrate noise generation and...

In this paper, the importance and perspective for the digitally-assisted analog and RF circuits are discussed, especially related to wireless transceivers. Digital calibration techniques for compensating I/Q mismatch, IM2, and LO impairments in cellular, 2.4GHz WiFi, and 60GHz WiGig transceivers are introduced with detailed analysis and circuit implementations. Future technology directions such...

A new method based on adaptive GA (genetic algorithm) and manual experience for sizing and optimizing the CMOS analog circuits is presented in this paper. In the method the simulation tool is called to produce the fitness of every circuit in a population. According to the evaluation of the fitness we can choose the better circuits. By adjusting the sizes of the transistor through GA and restric...

THIS special issue consists of papers which have been presented at the 23rd European Solid-State Circuits Conference, held September 16–18, 1997 in Southampton, U.K. Three hundred sixteen people attended this ESSCIRC conference, which has a strong focus on integrated circuit design, including sensor interfaces, various analog functions, communication circuits, mixed-signal systems, memories and...

A digital readout electronics scheme in CMOS technology is described for integration with micro-electro-mechanical (MEM) sensors on the same chip. The readout circuit is general in nature and can be employed with a variety of analog sensors. The presented scheme in CMOS technology is fully integrable with the multiple sensor outputs either in a chain or an array format and is capable of detecti...

This chapter shows the application of particle swarm optimization (PSO) to size analog circuits which are synthesized by a genetic algorithm (GA) from nullor-based descriptions. First, a historical description of the development of automatic synthesis techniques to design analog circuits is presented. Then, the synthesis of analog circuits by applying a GA at the transistor level of abstraction...

Continued scaling of CMOS technology affects both, the parameters and the characteristics of MOSFET and the integrated circuit built on them and introduces some new problems in analog design. The reduction of the gate length and the gate oxide thickness led to improvements in terms of chip area, speed and power consumption. At the same time, nonlinear output conductance, reduced voltage gain an...

This paper describes a transistor sizing methodology for both analog and digital CMOS circuits. Various techniques are used for power optimization in CMOS VLSI circuits. Transistor sizing is one of the important techniques for the determination of circuit performance. The aim of the power optimization is to minimize the power and power-delay product or the energy consumption of the circuit. Thu...

This paper examines issues in the analog CMOS circuit implementation of the soft competitive neural learning algorithm. Results of simulations based on actual measurements of previously fabricated analog components, primarily CMOS Gilbert multipliers, are presented. These results demonstrate that a generalized version of the soft competitive learning algorithm is capable of discovering appropri...