This paper discusses issues in the design of analog-todigital converters (ADCs) in nanoscale CMOS and introduces some experimental designs incorporating techniques to solve these issues. Technology scaling increases the maximum conversion rate, but it decreases the gain and the SNR. To maintain a high SNR level despite the lowvoltage operation, the power consumption needs to be increased. Becau...

Progress in CMOS device technology has motivated the design of high-performance analog integrated circuits in standard CMOS processes. In particular, the high speed of submicron CMOS devices make them attractive for a variety of analog applications, including data converters, switched capacitor circuits, and low noise amplifiers [1,2,16]. However, recent reports have indicated that the measured...

Optoelectronic integrated circuits can support thousands of integrated optical laser diodes and photodetectors bonded to a high-performance CMOS substrate, and can be used in the design of Multi-Terabit optical Local Area Networks. This paper describes the design of an integrated optoelectronic CMOS crossbar switch to interconnect approx. 128 parallel fiber ribbon optical links, each with 12 ch...

Monolithic integration of Microelectromechanical Systems (MEMS) directly within CMOS technology offers enhanced functionality for integrated circuits (IC) and the potential improvement system-level performance MEMS devices in close proximity to biasing sense circuits. While bulk CMOS-MEMS solutions involve post-processing chips define freely-suspended structures, there are key applications cond...

Superior electronic properties of graphene make it a substitute candidate for beyond-CMOSnanoelectronics in electronic devices such as the field-effect transistors (FETs), tunnel barriers, andquantum dots. The armchair-edge graphene nanoribbons (AGNRs), which have semiconductor behavior,are used to design the digital circuits. This paper presents a new design of ternary half a...

On-chip parasitic inductance inherent to the power supply rails has become significant in high speed digital circuits. Therefore, current surges result in voltage fluctuations within the power distribution networks, creating delay uncertainty. On-chip simultaneous switching noise should therefore be considered when estimating the propagation delay of a CMOS logic gate in high speed synchronous ...

Optimization of leakage power is essential for nanoscale CMOS (nano-CMOS) technology based integrated circuits for numerous reasons, including improving battery life of the system in which they are used as well as enhancing reliability. Leakage optimization at an early stage of the design cycle such as the register-transfer level (RTL) or architectural level provides more degrees of freedom to ...

We describe the design and development of a high-speed 8-channel hybrid integrated optical transceiver package with Clock and Data Recovery (CDR) circuits. The package concept has been developed to be compatible with microprocessor package technology and at the same time allow the integration of low cost, high-performance optical components. A 90nm CMOS optical transceiver chip, 850nm 10Gb/s Ga...

Some applications of wireless sensor networks (WSN) require long-term deployments and vanishingly-small unit volumes to make them cost effective and unobtrusive. Energyand area-efficient circuits, as well as eliminating offchip components, are critical to meeting these objectives. A conventional WSN node can be fully integrated in CMOS except for the battery, crystal reference, and antenna. Typ...

An AlGe eutectic wafer level bonding process is presented and characterized for heterogeneous integration of silicon photonics, CMOS integrated electronic circuits and active III-V components. Heterogeneous Integration of Photonics and CMOS The technology of silicon photonics integrated circuits (SiPIC) currently finds itself transitioning from research to industrial scale production [1]. The p...