Although CMOS Time-of-Flight Range Image Sensors have been recently realized, the fabrication process is modified by inserting an extra mask layer to allow efficient TOF dependent charge transfer. This work focuses on the selection procedure of amplifiers to be used in the design of the TOF pixel using the standard CMOS process. From our analysis, it is found that the Cascode amplifier is the b...

In this paper, a new CMOS power amplifier that can operate at 70 GHz is designed and developed. The advantages of using 70 GHz at millimeter wave (mmW) band is the huge amount of bandwidth available for various purposes whether they are in the cellular industry or manufacture devices such as high bandwidth wireless LAN and low attenuation of bandwidth frequencies around 70 GHz bands comparing w...

This paper reports the design of a highly-linear CMOS amplifier for Variable Gain Amplifier (VGA) applications. A better than –60dB 3rd harmonic distortion at differential output level of 1V peak-to-peak is obtained by utilizing a linearization scheme that does not rely on the active devices. The amplifier maintains 3dB bandwidth over 300MHz. A noise figure at 8.6dB is obtained with source impe...

This paper proposes a low voltage (±0.55V supply voltage) low power (44.65µW) high common mode rejection ratio (CMRR) differential amplifier (d.a.) with rail to rail input common mode range (ICMR), constant transconductance (gm) and enhanced frequency performance. Its high performance is obtained using a simple negative averaging method so that it cancels out the common mode input signals at th...

An ultra-low power CMOS image sensor is designed for endomicroscope applications. The chip will be fabricated through Global Foundries 0.18μm standard CMOS process with 1V power supply. The total power consumption is 6μW for 96×96 array with 5fps frame rate, where global amplifier consumes 3.3 μW, 10-bit SAR ADC consumes 900nW at 50kS/s, and on-chip digital processing further reduces IO power c...

Sense amplifiers are one of the very important peripheral components of CMOS memories. In a Hybrid Sense amplifier both current and voltage sensing techniques are used which makes it a better selection than a conventional current or voltage sense amplifiers. The hybrid sense amplifier works in three phases-Offset cancellation (200ps), Access phase (500ps) and Evaluation phase. The offset cancel...

As per the Moore’s law, there is an extreme increase in number of on chip devices, this increase in chip density results in power dissipation and thus the power utilization is unsatisfactory. So to avoid this problem the concept of Low Power system arises. As a part of microelectronics, it has been proposed to make the choice of minute circuit with attraction added by use of MOS cells. Since we...

A two-stage self-biased cascode power amplifier in 0.18m CMOS process for Class-1 Bluetooth application is presented. The power amplifier provides 23-dBm output power with a power-added efficiency (PAE) of 42% at 2.4 GHz. It has a small signal gain of 38 dB and a large signal gain of 31 dB at saturation. This is the highest gain reported for a two-stage design in CMOS at the 0.8–2.4-GHz frequen...

Three 12 bit, 40 MS/s pipelined analog-to-digital-converters (ADCs) are developed in 0.35μm CMOS process with 3.3V single power supply. The proposed ADCs architectures study the influence of the amplifier sharing technique in the power consumption and the main performances in the pipeline ADCs. Simulations results with extracted netlists are provided and show that the amplifier sharing techniqu...

In this paper, a low noise high gain CMOS amplifier for minute nerve signals is presented. By using a mixture of weakand strong inversion transistors, optimal noise suppression in the amplifier is achieved. A continuous-time offsetcompensation technique is utilized in order to minimize impact on the amplifier input nodes. The method for signal recovery from noisy nerve signals is presented. A p...