Reconfigurable architectures that tightly integrate a standard CPU core with a field-programmable hardware structure have recently been receiving increased attention. The design of such a hybrid reconfigurable processor involves a multitude of design decisions regarding the field-programmable structure as well as its system integration with the CPU core. Determining the impact of these design d...

In this paper we present HARE, a new hierarchical approach to register allocation and assignment for multiple issue load/store architectures. HARE makes extensive use of execution estimates and functional unit availability information to select values for spilling and to place the spill code in locations that minimize the increase in the overall execution time of the program. Incorporated in HA...

Set similarity join is a core operation for text data integration, cleaning, and mining. Previous research work on improving the performance of set similarity joins mostly focused on sequential, CPU-based algorithms. Main optimizations of such algorithms exploit high threshold values and the underlying data characteristics to derive efficient filters. In this paper, we investigate strategies to...

This paper examines the design of a 32-b GaAs Fast RISC microprocessor (F-RISC/I). F-RISC/I is a single chip GaAs HMESFET processor targeted for implementation on a multichip module (MCM) together with cache memories. The CPU architecture, circuit design, implementation, and testing are optimized for a seven-stage instruction pipeline implemented with GaAs super-buffered FET logic (SBFL). We ha...

The development of CPUs and of real-time systems based on them made it possible to use time at increasingly low resolutions. Together with the scheduling methods and algorithms, time organizing has been improved so as to respond positively to the need for optimization and to the way in which the CPU is used. This presentation contains both a detailed theoretical description and the results obta...

This paper considers the problem of register communication in the Multiscalar architecture, a novel paradigm for exploiting instruction level parallelism. The Multiscalar architecture employs a combination of hardware and software mechanisms to partition a sequential program into tasks, and uses control and data speculation to execute such tasks in parallel. Inter-task register dependencies rep...

Register file is a hot spot in contemporary microprocessors. As the number of instructions present in the processor at a given time increases, the size of the register file increases and it becomes a more important source of power dissipation inside the processor. Therefore it is important to pursue techniques that reduce the energy dissipation of register files. In this paper we present a tech...

Predicated execution is an efficient mechanism to avoid conditional constructs in application programs. In this paper we describe how an existing method for register binding can be extended to support predicated execution. The method exploits the combination of register constraints, resource and timing constraints and models the overlap of value lifetimes in a conflict graph. In our extension, ...

Developing countries have embarked on the promotion of “ICT access for all” through subsidized Information and Communication Technologies (ICTs), especially in underserviced areas of such countries. The main aim of the “ICT access for all” is to extend the communication services to the large areas of underserviced regions through subsidized communication services. In some instances, subsidies m...

If uniform coding (Gödelization) of potentially infinite sequences of numbers can be performed in PSPACEF, then PSPACE = EXPTIME 6= EXPSPACE = 2-EXPTIME, and, for all p, we have p−EXPSPACE = p+1-EXPTIME; if it can be performed in LINSPACEF, we also have LINSPACE = DTIME(2); the proof fails, when relativized to oracle-TM’s. A by-product of this research is that PTIMEF is not closed under number-...