Flexibility is one mandatory aspect of channel coding in modern wireless communication systems. Among other things, the channel decoder has to support several code lengths and code rates. This need for flexibility applies to polar codes that are considered for control channels in the future 5G standard. This paper presents a new generic and flexible implementation of a software Successive Cance...

The application of turbo codes in modern communication systems makes decoding a time and power consuming task. It is known that analog decoder are superior to digital decoder designs in terms of speed and power consumption. The fact that a modification of a single code parameter like the block length requires a new analog decoder implementation, in combination with a complexity, which grows lin...

An all-MOS analog tail-biting MAP decoder is presented for an (8,4) Hamming code. The decoder implements a probability propagation algorithm using subthreshold CMOS networks. Physical results verify the expected behavior of the decoder and demonstrate robustness of analog decoding circuits. The authors of [l] present a class of analog VLSI circuits which can be used to implement a general proba...

In this paper, we describe the VLSI implementation of a JPEG decoder. The implementation used custom designed hardware as well as synthesized components. We have implemented a Huffman decoder, a run length decoder, a booth multiplier alongwith a custom datapath consisting of a register file, shifter and ALU.

Delft University of Technology Faculty of Electrical Engineering, Mathematics and Computer Science CE-MS-2003-13 Entropy Decoding is an essentially sequential task. Executing this task on a processor that benefits from Instruction Level Parallelism (ILP), Data Level Parallelism (DLP) or both requires an efficient implementation of Entropy Decoding. Entropy Decoding forms the part of MPEG-2 Deco...

We introduce the notion of innovations for Viterbi decoding of convolutional codes. First we define a kind of innovation corresponding to the received data, i.e., the input to a Viterbi decoder. Then the structure of a Scarce-State-Transition (SST) Viterbi decoder is derived in a natural manner. It is shown that the newly defined innovation is just the input to the main decoder in an SST Viterb...

In this paper, we present a low power hybrid low-density-parity-check (LDPC) decoder hardware implementing layered min-sum decoding algorithm for IEEE 802.11n Wireless LAN Standard. The LDPC decoder hardware, which has 27 check node datapaths and 24x162 variable node memory, is implemented in Verilog HDL and verified to work correctly in a Xilinx Virtex II FPGA. For 648 block length and 1/2 cod...

A per-survivor adaptive interference cancellation (PSAIC) decoder is proposed for group decoding of a space–time trellis-coded DS-CDMA system. To mitigate error propagation by tentative decisions, persurvivor processing is introduced to a group decoder with adaptive interference cancellation. It is shown that the proposed decoder outperforms conventional decoders without much increase of decodi...

Genetic algorithms are successfully used for decoding some classes of error correcting codes, and offer very good performances for solving large optimization problems. This article proposes a new decoder based on Serial Genetic Algorithm Decoder (SGAD) for decoding Low Density Parity Check (LDPC) codes. The results show that the proposed algorithm gives large gains over sum-product decoder, whi...