نتایج جستجو برای: delay locked loop dll

تعداد نتایج: 269676  

2014

In the literature, surfing technique has been proposed for single ended wave-pipelined serial interconnects to increase the data transfer rate. In this paper a novel surfing technique is proposed for differential wave-pipelined serial interconnects, which uses a 'Controllable inverter pair' for surfing. To evaluate the efficiency of this technique, a transceiver with transmitter, receiver, dela...

2017
Kimia Shamaei Joe Khalife Souradeep Bhattacharya Zaher M. Kassas

A receiver for positioning with LTE signals, which could mitigate multipath in a computationally efficient fashion is presented. The receiver uses an orthogonal frequency division multiplexing (OFDM)–based delay-locked loop (DLL) to track the received LTE signals. The ranging error performance in an additive white Gaussian noise (AWGN) channel is evaluated numerically. The results demonstrate r...

2006
Guojiang Gao

This paper proposes a novel architecture for ultra-tight integration of a High Sensitivity Global Positioning System (HSGPS) receiver with an Inertial Navigation System (INS), to address the issue of GPS tracking and positioning in degraded signal environments. By enhancing signal tracking loops in receivers through the use of optimal controllers/estimators and aiding from external source such ...

Journal: :Applied sciences 2023

To meet the demand for high-precision positioning in commercial industrial internet scenarios, 3GPP introduced Positioning Reference Signal (PRS) 5G standard. However, PRS signal occupies specific time and frequency resources transmission systems, limiting efficiency of communication to some extent. In this regard, we propose a NR Co-Band model that allows superimposition signals on low-power m...

Journal: :IEEE Trans. on Circuits and Systems 2007
Chi-Nan Chuang Shen-Iuan Liu

A 0.5–5 GHz wide-range multiphase delay-locked loop (MDLL) with a calibrated charge pump is presented. A multiperiod-locked technique is used to enhance the input frequency range of a MDLL and avoid the harmonic-locked problem. The charge pump current is also calibrated to reduce the static phase error. This MDLL has been fabricated in 0.13m CMOS process. The measured root-mean-square and peak-...

2014
Krishna Priya

The traditional analog signal processing is expected to progressively substituted by the processing times of the digital domain in the VLSI .Within this novel paradigm ,digitally controlled delay lines should play the vital role in the digital-toanalog converters ,and in analog intensive circuits. From a practical point of view, nowadays, DCDL is a key block in the many applications like All Di...

Journal: :CoRR 2015
Naveen Kadayinti Maryam Shojaei Baghini Dinesh Kumar Sharma

A clock synchronizing circuit for repeaterless low swing interconnects is presented in this paper. The circuit uses a delay locked loop (DLL) to generate multiple phases of the clock, of which the one closest to the center of the eye is picked by a phase detector loop. The picked phase is then further fine tuned by an analog voltage controlled delay to position the sampling clock at the center ...

2005
Tuvia Liran Ran Ginosar

An improved architecture for all digital Delay Locked Loop (ADDLL) had been developed and implemented for several applications and design methodologies. In most cases it can be based on standard cells only. Several techniques are used to minimize the jitter, achieving less than 40pS (peak) for 0.13μ technology. The frequency range is very wide, exceeding 500MHz. For 0.13μ core, the area is 0.01...

2010
Mohamed G. El-Tarhuni

PN code tracking is one of the most important factors that affect the performance of spread spectrum receivers. It is desirable to maintain PN code tracking for a long period of time and with high accuracy. This paper presents a non-coherent digital delay-locked loop (DLL) for code tracking in direct-sequence spread spectrum (DS-SS) systems. The proposed technique utilizes three non-coherent co...

Journal: :IEICE Transactions 2008
Ching-Yuan Yang Chih-Hsiang Chang Wen-Ger Wong

A high-speed triangular-modulated spread-spectrum clock generator using a fractional phase-locked loop is presented. The fractional division is implemented by a nested fractional topology, which is constructed from a dual-modulus divide-by-(N–1/16)/N divider to divide the VCO outputs as a first division period and a fractional control circuit to establish a second division period to cause the o...

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