Predicting depth is an essential component in understanding the 3D geometry of a scene. While for stereo images local correspondence suffices for estimation, finding depth relations from a single image is less straightforward, requiring integration of both global and local information from various cues. Moreover, the task is inherently ambiguous, with a large source of uncertainty coming from t...

Gårding et al. (Vis Res 1995;35:703-722) proposed a two-stage theory of stereopsis. The first uses horizontal disparities for relief computations after they have been subjected to a process called disparity correction that utilises vertical disparities. The second stage, termed disparity normalisation, is concerned with computing metric representations from the output of stage one. It uses vert...

Materials such as waste tire chips were widely used to improve the strength of soil. The objective of this study is to discuss the residual strength or steady-state behavior of sand-waste tire chip mixtures. A series of undrained monotonic triaxial compression tests were conducted on reconstituted saturated specimens of sand and sand-tire chip mixtures with variation in the tire-chip contents f...

the aim of this study is experimental assay of sensitivity and stability of a bimetallic silver/gold spr sensor chip. this chip utilizes the sensitivity of the silver and the stability of the gold. moreover, the silver layer (instead of usual cr or ti layer) was used as an adhesive intermediate layer between the gold layer and the glass substrate. the optimization of the gold/silver thickness u...

The scaling of minimum feature sizes down to nanometer range and the spiraling frequencies in GHz scale has lead to system-on-a-chip (SOC) implementation for many emerging applications. To utilize the unprecedented computing power of over billion transistors on each SOC die many integrated circuit (IC) implementations have been adopting multi-core strategies instead of single-core implementatio...

The trend for multicore CPUs is towards increasing core count. One of the key limiters to scaling will be the on-chip directory cache. Our work investigates moving portions of the directory away from the cores, perhaps to off-chip DRAM, where ample capacity exists. While suchmulti-level directory caches exhibit increased latency, several aspects of directory accesses will shield CPU performance...

Technology scaling into subnanometer range will have impact on the manufacturing yield and quality. At the same time, complexity and communication requirements of systems-on-chip (SoC) are increasing, thus making a SoC designer goal to design a fault-free system a very difficult task. Network-on-chip (NoC) has been proposed as one of the alternatives to solve some of the on-chip communication p...