A novel charge-based comparator and folding circuit are presented. Correlated double sampling comparison is performed using a log-domain integrator, implemented by a subthreshold MOS transistor with the source coupled to a capacitor. The circuit produces a current that is a logistic function of the change in voltage on the gate, with an input-referred offset voltage that is a logarithmic functi...

Precise discrimination between similar cellular states is essential for autonomous decision-making scenarios, such as in vivo targeting of diseased cells. Discrimination could be achieved by delivering an effector gene expressed under a highly active context-specific promoter. Yet, a single-promoter approach has linear response and offers limited control of specificity and efficacy. Here, we co...

In this paper the programmable Digital Down Converter (DDC) structure is proposed which can be used in digital receivers that meets GSM specifications in wireless communications systems. The major advantage of the proposed DDC is that it does not have the passband drop which is very often associated with the Cascaded Integrator-Comb (CIC) based DDCs. Another improvement of the proposed DDC stru...

We present a new optical system design for a projector with a single digital micromirror device (Texas Instruments Digital Micromirror Device) that improves on previous designs in terms of optical efficiency, uniformity, and contrast while yielding a low-profile and compact system. A rod integrator is incorporated with a compact relay system to maximize light efficiency and to increase illumina...

A scaling-friendly approach for the low-power calibration of oversampled analog-to-digital (A/D) systems is presented. A 22-dB amplifier relaxes the design constraints of the analog front-end (AFE). The integrator nonidealities in the AFE of the sigma-delta (ΣΔ) ADC are calibrated using a multi-rate polyphase least-mean squares (LMS) algorithm. The proposed half(fs/2) and quarter-rate (fs/4) LM...

This paper presents an excitatory CMOS power consumption and circuit size, which is ideal for integrator is built using operational amplifier. This circuitry is realized in TSMC 0.18μm CMOS Technology. Switched Capacitor (SC) integrator circuit The SC integrator correlated double

Due to great value of the time constant of the integrator circuit, a hardware defined PWM (Pulse Width Modulation) signal makes it possible to build a Digital to Analog Converter (DAC) characterized by a relatively long response time. An attempt at creating the software defined PWM signal leads to increased response time of the DAC converter with a coefficient several hundred times longer than ...

This paper presents an OTA-less 2nd-order VCO-based CT ΔΣ modulator featuring a passive integrator that makes use of the VCO’s inherent parasitic effect. A low-power capacitive feedback technique is also presented for robust loop compensation. Fabricated in 40nm CMOS, the prototype occupies 0.028mm2 of active area and consumes 524μW when sampling at 330MHz. The ΔΣM achieved peak Walden FoM of 1...

This contribution deals with a fully digital multirate radio receiver with IF sampling. Timing correction and sample rate conversion are performed by a polynomial interpolator. By performing interpolation prior to matched filtering a significant reduction in complexity may be achieved. Low degradations are attainable when the receiver design parameters are carefully chosen. If this is not possi...

Abstract We propose and analyse a numerical integrator that computes low-rank approximation to large time-dependent matrices are either given explicitly via their increments or the unknown solution matrix differential equation. Furthermore, is extended of tensors by Tucker fixed multilinear rank. The proposed different from known projector-splitting for dynamical approximation, but it retains i...