Abstract –In many measurement applications, it is required to have digital-to-analog converters (DAC). All DACs use a reconstruction (anti-imaging) filter as the final step in the conversion process. Without this filter, generating a continuousamplitude signal would not be possible. This paper presents a new theoretical concept of a post-DAC continuous-time filter. The proposed filter was desig...

Digital-to-analog (D/A) converters (or DACs) are one the fundamental building blocks of wireless transmitters. In order to support the increasing demand for high-data-rate communication, a large bandwidth is required from the DAC. With the advances in CMOS scaling, there is an increasing trend of moving a large part of the transceiver functionality to the digital domain in order to reduce the a...

This paper proposes a reconfigurable current steering digital to analog converter (DAC). The differential non-linearity error (DNL) of the DAC is estimated on-chip. This is used to reconfigure the switching sequence to get a lower integral nonlinearity error (INL). A 10 bit segmented DAC along with the associated circuits for DNL estimation was designed and fabricated using 0.35μm CMOS technolo...

Multi-bit sigma-delta modulators are widely used in analog-to-digital conversion especially in the modern deep-submicron CMOS process. As the quantizer resolution of modulators increases, the SNR performance improves. However, the feedback DAC has to maintain high linearity. The general practice to achieve that is to use dynamic element matching (DEM). The methodology proposed in this paper wil...

A major drawback of delta-sigma modulation is the high oversampling ratios required, especially for single-bit quantization. Accordingly, much of the research in the area has focused on lowering the sampling rate through various parallelization approaches. However, this research has been overwhelmingly concentrated on continuous and discrete-time analog modulator implementations for A/D convert...

A Built-In Self-Test (BIST) approach that is designed to test the analog portion of mixed-signal systems is described. The majority of the BIST circuitry is located in the digital domain to minimize performance impact on the analog circuitry as well as to facilitate easy and automated synthesis of the BIST circuitry. The BIST approach has been implemented in parameterized VHDL for inclusion in ...

An oversampled digital-to-analog converter (DAC) with a 100-dB A-weighted dynamic range is presented. It uses a switched-capacitor (SC) array to transfer the sampled charges directly into the headphone driver. The overall DAC gain is precisely controlled by a novel reference stage. A new dynamic element matching algorithm, based on split-set data-weighted averaging (SDWA), is used to improve th...

This paper proposes an approach for designing a R-2R 10 bit Digital to Analog Converter (DAC) which could be made to operate at low voltage supply by efficiently exploiting the cascaded Operational Amplifier (Op-Amp) architecture. The DAC operates at a 3V power supply with a settling time of 50-100ns , dynamic range of around 50-60 dB for signals upto a frequency of 10Mhz. Graph & simulation re...

This paper describes sampling clock jitter effects in digital-to-analog converters. A formula for the output error power due to sampling clock jitter for a sinusoidal input is derived and verified by numerical simulations, and its spectrum characteristics is shown. Also its effects on DAC SNR is clarified by numerical simulation as follows: (i) When the total noise power outside as well as insi...