This paper presents a design method of AND-OREXOR three-level networks, where single two-input EXOR gate is used for each output. The network realizes an EXOR of two sum-of-products expressions (EX-SOP): F1 F2, where F1 and F2 are sum-ofproducts expressions (SOPs). The problem is to minimize the total number of di erent products in F1 and F2. A heuristic optimization algorithm is presented, and...

| The use of XOR gates has shown several advantages in modern circuit design, e.g. smaller representation size and better testability. In this paper we consider power consumption in XOR dominated circuits and compare such designs with traditional AND/OR logic. We investigate the suitability of using diierent delay models such as unit delay, fanout delay, and random delay in power estimation of ...

In this chapter, we introduce a generic Internet trading framework for online auctions. We present the requirements and service of the framework. A generic OR/XOR bidding language that can express different OR/XOR combinations is adopted for Web interfaces. The framework is implemented with free open-source technologies already successfully tested in industries. Researchers can use the platform...

This paper aims at comparing multiplication algorithms over Fpm on FPGA. Contrary to previous surveys providing the reader with an estimate of both area and delay in terms of XOR gates, we discuss placeand-route results which point out that the choice of an algorithm depends on the irreducible polynomial and on some architectural parameters. We designed a VHDL code generator to easily study a w...

A fundamental lemma of Yao states that computational weakunpredictability of Boolean predicates is amplified when the results of several independent instances are XOR together. We survey two known proofs of Yao’s Lemma and present a third alternative proof. The third proof proceeds by first proving that a function constructed by concatenating the values of the original function on several indep...

We consider a bidirectional ring of n processors, where processors are anonymous, i.e., are indistinguishable. In this model it is known that “most” functions (in particular XOR and orientation) have worst case message complexity @(n’) for asynchronous computations, and O(n log n) for synchronous computations. The average case behavior is different; an algorithm that computes XOR asynchronously...

Temporal reasoning is widely used within both Computer Science and A.I. However, the underlying complexity of temporal proof in discrete temporal logics has led to the use of simplified formalisms and techniques, such as temporal interval algebras or model checking. In this paper we show that tractable sub-classes of propositional linear temporal logic can be developed, based on the use of XOR ...

This paper presents two new constructions for the secret color images sharing schemes .One is a (n, n) threshold scheme, which can be constructed based on XOR operation. The other is a (2, n) threshold scheme, which can be constructed by using AND and XOR operations. The two schemes have no pixel expansion, and the time complexity for constructing shared images is O(k1n), excluding the time nee...

In this paper, we present a new synthesis feature namely, “Xor matching”, and the foldback product term synthesis for Complex Programmable Logic Devices (CPLD) architecture that is based on PAL-like macrocells. Our goal is to use the Xor gate and the foldback terms, (or shareable expander − Altera equivalent terminology [17]), available in each macrocell for minimizing the number of macrocells ...

Diierential cryptanalysis is a method of attacking iterated mappings which has been applied with varying success to a number of product ciphers and hash functions 1, 2]. Let : Z c 2 Z m 2 ! Z m 2 be a mapping that consists of c `control' bits and m `data' bits. The mapping mapping contains 2 c m-bit permutations i : Z m 2 ! Z m 2 ; 0 i 2 c ? 1, one of which is selected (multiplexed) by the cont...