We propose a novel test coverage measure for continuous and hybrid systems, which is defined using the star discrepancy notion. We also propose a test generation method guided by this coverage measure. This method was implemented in a prototype tool that can handle high dimensional systems (up to 100 dimensions).

This paper is devoted to the derivation of distinguishing sequences for timed Finite State Machines (FSM). Such distinguishing sequences are used when deriving a test suite for a timed FSM with the guaranteed fault coverage.

We propose a method of partitioning the set of all ip-ops in a circuit for multiple clock testing. In the multiple clock testing, ip-ops are partitioned into diierent groups and each group of ip-ops has an independent clock control. In our method, we use a test generator assuming an independent clock control for each ip-op. We than determine correlation between clock activity for all pairs of i...

Dynamic test sequence compaction is an effective means of reducing test application time and often results in higher fault coverages and reduced test generation time as well. A new algorithm for dynamic test sequence compaction is presented that uses genetic techniques to evolve test sequences. Test sequences provided by a test generator and previously evolved sequences already included in the ...

The test of Σ∆ modulators is cumbersome due to the high performance they reach. Moreover, technology scaling trends raise serious doubts on the intra-die repeatability of devices. Increase of variability will lead to an increase in parametric faults difficult to detect. In this paper, a designoriented testing approach is proposed to perform simple and low-cost detection of variations in importa...

This paper presents a new approach to Automatic Test Pattern Generation for sequential circuits. Traditional topological algorithms nowadays are able to deal with very large circuits, but often fail when highly sequential subnetworks are found. On the other hand, symbolic techniques based on Binary Decision Diagrams proved themselves very efficient on small or medium circuits, no matter their s...

Generation of minimum-length test sequences (MLTS) for FSM/EFSM models has been the focus of recent studies. Although it aims to optimize test cycles and expedites product marketing, an MLTS may fail to reveal potential discrepancies between an implementation and its specification. In this paper, MLTS methods combining FSM/EFSM models and pseudo random test generation techniques to enhance test...

In this paper, we address the problem of evaluating the effectiveness of test sets to detect crosstalk defects in interconnects of deep sub-micron circuits. The fast and accurate estimation technique will enable: (a) the evaluation whether legacy functional, delay, and boundary scan tests can be used for effective interconnect crosstalk defect coverage, (b) development of crosstalk tests if the...

⎯ In this paper, we present a comprehensive experimental assessment of fault coverage for a fault-tolerant VLIW processor, which consists of the error detection, error rollback recovery and reconfiguration mechanisms. We implement the proposed design of fault-tolerant VLIW in VHDL and employ the fault injection to investigate the effects of fault duration, workload variation and the number of r...

A methodology for the determination of decompression hardware that guarantees complete fault coverage for a unified compaction/compression scheme is proposed. Test cube information is utilized for the determination of a near optimal decompression hardware. The proposed scheme attains simultaneously high compression levels and reduced pattern counts through a linear decompression hardware. Signi...