This paper addresses the problem of the validation of fault tolerance mechanisms during the design of fault-tolerant computing systems. It presents an integrated environment for applying fault injection into simulation models encompassing various levels of abstraction. First, the expected benefits of the approach are clearly identified in relation to other fault injection methods available. The...

This paper discusses the important role of fault grouping in a parallel 32-bit fault simulator such as PROOFS. Three algorithms are presented which dynamically order the fault list during fault simulation to determine how the faults get grouped together. The dynamic fault grouping algorithms were incorporated into PROOFS and tested on benchmark circuits. The algorithms showed a marked reduction...

In this paper we present the specification backpropagation technique which enables one to derive the constraint of an internal functional block with respect to a given DC specification for an analog/mixed-signal system. Based on this technique, we implement an efficient fault simulator which reduces the required efforts by (1) removing undetectable faults from the fault list, and (2) performing...

In diagnostic testing faults detectable by test vectors are partitioned into groups. This partitioning is such that a fault is distinguishable from faults in all other groups, but is indistinguishable from those in its own group. Diagnostic fault coverage (DC) is defined as the number of fault groups divided by the total number of faults. We present a new diagnostic fault simulation algorithm t...

The areas of analog circuit fault simulation and test generation have not witnessed the same degree of success as their digital counterparts. This is due mainly fo the complexity of analog behavior and the lack of a fault model. We present a new Jicnctional fault modeling technique called the perturbation fault model. The perturbation fault model is based on an estimation of the distance betwee...

As can be seen in Figure 6.1, there is a stage called test development where it basically consists of three activities; test generation, fault simulation and design for testability implementation. Test generation is a method of generating an input sequence that can distinguish between good chip and defective chip when the input sequence (test sequence) is applied to the chip using a tester. Fau...

Distributed DEVS simulation plays an important role in solving complex problems for its reuseability, and composability of component models. Using MPI to be the communication middleware, the distribution increases the performance. But even the tiny faults of computing resources can lead to crash. Hence Fault Tolerant is necessary to maintain the simulation reliability. This paper introduces a D...

An approach to test optimization in switched-capacitor systems based on fault simulation at switch-level is presented in this paper. The advantage of fault simulation at this granularity level is that it facilitates test integration as early as possible in the design of these systems. Due to their mixed-signal nature, both catastrophic and parametric faults must indeed be considered for test op...

This paper presents a fault simulation algorithm that uses efficient partial reconfiguration of FPGAs. The methodology is particularly useful for evaluation of BIST effectiveness, and for applications in which multiple fault injection is mandatory, such as safety-critical applications. A novel fault collapsing methodology is proposed, which efficiently leads to the minimal stuck-at fault list a...

Quantum-dot cellular automata (QCA) are an emerging technology and a possible alternative for semiconductor transistor based technologies. A novel fault-tolerant QCA full-adder cell is proposed: This component is simple in structure and suitable for designing fault-tolerant QCA circuits. The redundant version of QCA full-adder cell is powerful in terms of implementing robust digital functions. ...