Fault tolerance techniques are used to allow computer systems to continue correct operation despite component failure. Hardware-supported concurrent error-detection and limited fault tolerance in system components, as implemented by coding or replication, are often required. Detection latency can be reduced by increasing the visibility of internal module state using compressed ‘‘signatures’’ of...

Quantum-dot Cellular Automata (QCA) is an emerging and promising technology that provides significant improvements over CMOS. Recently QCA has been advocated as an applicant for implementing reversible circuits. However QCA, like other Nanotechnologies, suffers from a high fault rate. The main purpose of this paper is to develop a fault tolerant model of QCA circuits by redundancy in hardware a...

Keywords: Single event effect Fault tolerance Triple and double modular redundancy Latchup protection switch ASIC design a b s t r a c t The paper presents CMOS ASICs which can tolerate the single event upsets (SEUs), the single event transients (SET), and the single event latchup (SEL). Triple and double modular redundant (TMR and DMR) circuits in combination with SEL protection switches (SPS)...

The move towards nanoscale Integrated Circuits (ICs) increases performance and capacity, but poses process variation and reliability challenges which may cause several faults on routers in Networks-on-Chips (NoCs). While utilizing healthy routers in an NoC is desirable, faulty regions with different shapes are formed gathering faulty routers. Fault regions can be used to lead the fault-tolerant...

Reversible logic is becoming an important research area which aims mainly to reduce power dissipation during computing. In this paper we introduce a new parity preserving reversible gate PPPG (a 5x5 gate). This gate is universal in the sense it can synthesize any arbitrary Boolean function. It is also a parity preserving gate in which the parity of input matches the parity of the output. This p...

The move towards nanoscale circuits poses new challenges to circuit design. As the dimensions shrink, it is becoming increasingly difficult to control the variance of physical parameters in the manufacturing process, for instance the concentration of dopants, the thickness of the gate and the insulation oxides, the width and thickness of metal wires, etc. This results in decreased yield which i...

ÐThis paper addresses the problem of synthesizing fault-secure controller/data path circuits from behavioral specifications. These circuits are guaranteed to either produce the correct output, or to flag an error. We use an iterative improvement-based behavioral synthesis framework that performs functional unit selection, clock selection, scheduling, and resource sharing with the aim of minimiz...

To explore the possibilities of a near-term intermediate-scale quantum algorithm and long-term fault-tolerant computing, fast versatile circuit simulator is needed. Here, we introduce Qulacs, for circuits intended research purpose. We show main concepts explain how to use its features via examples, describe numerical techniques speed-up simulation, demonstrate performance with benchmarks.

This article may be used for research, teaching and private study purposes. Any substantial or systematic reproduction, redistribution , reselling , loan or sub-licensing, systematic supply or distribution in any form to anyone is expressly forbidden. This paper presents a new hybrid fault-tolerant architecture for robustness improvement of digital CMOS circuits and systems. It targets all kind...

Reversible computation plays an important role in the synthesis of circuits having application in quantum computing, low power CMOS design, bioinformatics and nanotechnology-based systems. Conventional logic circuits are not reversible. A reversible circuit maps each input vector, into a unique output vector and vice versa. We demonstrate how the well-known and very useful, Toffoli gate can be ...