This paper introduces the Field-Programmable Learning Array, a new paradigm for rapid prototyping of learning primitives and machinelearning algorithms in silicon. The FPLA is a mixed-signal counterpart to the all-digital Field-Programmable Gate Array in that it enables rapid prototyping of algorithms in hardware. Unlike the FPGA, the FPLA is targeted directly for machine learning by providing ...

New markets are emerging for the fast growing field-programmable gate array (FPGA) industry. Standard and fair benchmarking practices are necessary to evaluate FPGA systems and determine their potential to support target applications. This paper provides an extensive survey of FPGA benchmarks in both academia and industry.

Reconfigurable hardware is emerging as the best option for the efficient implementation of complex and computationally expensive signal processing algorithms. Reconfigurable hardware exploits the benefit of high of computational efficiency of hardware as well as flexibility of software implementation. Field Programmable Gate Array (FPGA) which finds wide range of applications in the field of si...

Abstract. Hummingbird is a novel ultra-lightweight cryptographic algorithm aiming at resource-constrained devices. In this work, an enhanced hardware implementation of the Hummingbird cryptographic algorithm for low-cost Spartan-3 FPGA family is described. The enhancement is due to the introduction of the coprocessor approach. Note that all Virtex and Spartan FPGAs consist of many embedded memo...

We present a runtime environment that partially reconfigures and executes hardware tasks on Xilinx Virtex. To that end, the FPGA’s reconfigurable surface is split into a varying number of variable-sized vertical task slots that can accommodate the hardware tasks. A bus-based communication infrastructure allows for task communication and I/O. We discuss the design of the runtime system and its p...

These last thirty years were outstanding by the revolution of technology possibilities in the field of digital electronics and this, as much as within context of programmable solutions like (Microcontroller, DSP,...etc), than of reconfigurable solutions (CPLD, FPGA). Among all these possibilities, Field Programmable Gate Array (FPGA devises) is a good compromise between the advantage of the fle...

This paper is devoted to the design of a 258bit multiplier for computing pairings over Barreto-Naehrig (BN) curves at 128-bit security level. The proposed design is optimized for Xilinx field programmable gate array (FPGA). Each 258-bit integer is represented as a polynomial with five, 65 bit signed integer, coefficients . Exploiting this splitting we designed a pipelined 65-bit multiplier base...

This white paper presents the implementation of a high-performance HyperTransport-enabled Network Interface Controller (NIC), named Virtualized Engine for Low Overhead (VELO). The direct connect architecture and efficiency of HyperTransport produce an NIC capable of sub-microsecond latency. The prototype implemented on a Field Programmable Gate Array (FPGA) delivers a communication latency of 9...