Clustered voltage scaling scheme is an effective method of power consumption reduction without performance degradation. One of the main issues in this scheme is performance and power penalties due to insertion of level converting flip-flops at the interface from low-supply to high supply clusters to simultaneously perform latching and level converting functions. A new level converting flip-flop...

In this paper, the proposed flip-flop reduces power consumption by reducing the clock switching power that was wasted otherwise. Unlike many other gated flip-flops, the proposed gated flip-flop has state retention property to save power and to switch circuit between idle and active modes smoothly. The feedback path is also improved in the proposed flip-flop to decrease power dissipation. The pr...

The consumption of power has become an important issue in modern VLSI design. Power consumption can be reduced by replacing some flip-flops with fewer multi-bit flip-flops. Multi-bit flip-flop is one of the methods for clock power consumption reduction. This project focuses on reduction of power using multi-bit flipflops by clock synchronization. Two single bit flip-flops are synchronized with ...

Suppression of apoptosis is one of the hallmarks of carcinogenesis. Tumor cells endure apoptotic pressure by overexpressing several antiapoptotic proteins, and FLICE inhibitory protein (FLIP) is one of the important antiapoptotic proteins that have been shown to be overexpressed in various primary tumor cells. FLIP has two death-effector domains in tandem, mimicking the prodomain of procaspase-...

Although c-FLIP has been identified as an important player in the extrinsic (death receptor-induced) apoptosis pathway, its endogenous function in mature T lymphocytes remains undefined. c-FLIP may inhibit or promote T cell death as previous data demonstrate that the c-FLIP(L) isoform can promote or inhibit caspase 8 activation while the c-FLIP(S) isoform promotes or inhibits T cell death when ...

Most digital systems textbooks treat the topic of converting one flip flop to another by simply giving the student certain simple conversion circuits, such as the use of an inverter between the R and S inputs of an RS flip flop to form a D flip flop, or tying together the inputs of a JK flip flop to make a T flip flop. However, a more general, but very simple, methodology for flip flop conversi...

This paper describes an original circuit design of a static CMOS double-edge triggered flip-flop (DETFF). Doubleedge triggered (DET) flip-flops are bistable flip-flop circuits in which data is latched at either edge of the clock signal. Using such flip-flops permits the rate of data processing to be preserved while using lower clock frequency (as compared to a circuit with single-edge triggered...