BACKGROUND Flip-flops and sandals are popular choices of footwear due to their convenience. However, the effects of these types of footwear on lower extremity biomechanics are still poorly understood. Therefore, the objective of this study was to investigate differences in ground reaction force (GRF), center of pressure (COP) and lower extremity joint kinematic and kinetic variables during leve...

Pulse-triggered flip-flops are mainly used to improve speed of operation (pipeline speed), though flip-flop robustness and system timing closure are challenging in a wide range of supply voltages. Usually pulse-triggered flip-flops have specific structures and transistor sizes to optimize the system performance. The transistor size, topology, and threshold voltage of the flip-flop make the timi...

Abstract: Power consumption is considered as one of the important challenge in modern VLSI design along with area and speed consideration. Flip flop plays very important role in digital systems. In this paper comparative study of four different flip flops which includes pulse triggered as well as conditional technique flip flop such as IP-DCO, MHLFF, CPSFF, and CPFF topologies in sub threshold ...

Clustered voltage scaling scheme is an effective method of power consumption reduction without performance degradation. One of the main issues in this scheme is performance and power penalties due to insertion of level converting flip-flops at the interface from low-supply to high supply clusters to simultaneously perform latching and level converting functions. A new level converting flip-flop...

This paper presents a fast and exact simulation algorithm for a general Gaussian Markov Random Field (GMRF) defined on a lattice, . For a neighborhood, the algorithm has initializationcost of flops and exact samples are then available using flops. Conditioned samples on general constraints costs only extra flops. The algorithm is easy to generalize to non-rectangular lattices, compute the log-l...

This paper describes an original circuit design of a static CMOS double-edge triggered flip-flop (DETFF). Doubleedge triggered (DET) flip-flops are bistable flip-flop circuits in which data is latched at either edge of the clock signal. Using such flip-flops permits the rate of data processing to be preserved while using lower clock frequency (as compared to a circuit with single-edge triggered...

A new flip-flop design using a double-pulsed static latch is presented. The flip-flop has only a single stage of logic in the critical path and as a result is up to three times faster than the fastest previously known flip-flops, while consuming approximately the same energy as the lowestpower flip-flops. The flip-flop has asymmetric timing properties which make it a good match to skewed logic ...

This paper addresses the issue of reducing test application time in sequential circuits with partial scan using a single clock configuration without freezing the state of the non-scan flip-flops. Experimental results show that this technique significantly reduces test application time. Further, we study the effect of ordering the scan flip-flops on the test vector length and also present a non-...

flip-flop circuit technique has been designed. CMOS new flip-flop circuit with CMOS domino logic which, All the flip-flops were designed using UMC 180. Recognize standard circuit symbols for D Type flip-flops. though can be largely prevented by using the Edge Triggered D Type flipflop illustrated in Fig 5.3.3. locked loop, using 32 nm CMOS technology. Here we design D flipflop for Phase locked ...

In this paper, we correlated various Master and slave flip-flops i.e., single edge triggered flipflops. The low-power flip-flops have place utmost necessary elements all the range of the constructing static or successive circuits. We accomplish the comparison for their performance, Delay, Rise time, Fall Time and Power dissipation. Because Power confide in the number of transistors in the circu...