A fine-grained reconfigurable architecture based on double gate technology is presented. The logic function operating on the first gate of a double gate (DG) transistor is reconfigured by altering the bias on its second gate. A compact reconfigurable cell is proposed that merges two stacked 3-state resonant tunneling devices and non-silicon transistors and “hides” the cost of reconfiguration by...

We have fabricated silicon-on-insulator ~SOI! transistors with an ultrathin Si channel of ;5 nm, tunneling gate oxide of ;1 nm, and 100 nm gate length. In addition to good transistor characteristics, these same devices exhibit additional functionality at low temperature. The drain current ID exhibits steps near the turn-on threshold voltage as a function of the backgate VBG bias on the substrat...

The significance of optimization of gate–source/drain extension region (also known as underlap design) in double gate (DG) silicon-on-insulator (SOI) FETs to improve the linearity performance of a low power folded cascode operational transconductance amplifier (OTA) is described. Based on a new figure-of-merit (FoM) involving AV , linearity, fT and dc power consumption PDC , the paper presents ...

High-performance GaAs metal-insulator-semiconductor field-effect-transistors MISFETs fabricated with very thin self-assembled organic nanodielectrics (SANDs), deposited from solution at room temperature, are demonstrated. A submicron gate-length depletion-mode n-channel GaAs MISFET with SAND thicknesses ranging from 5.5 to 16.5 nm exhibit a gate leakage current density 10−5 A/cm2 at a gate bias...

We study field-effect transistors realized from VO2 nanobeams with HfO2 as the gate dielectric. When heated up from low to high temperatures, VO2 undergoes an insulator-to-metal transition. We observe a change in conductance ( 6%) of our devices induced by gate voltage when the system is in the insulating phase. The response is reversible and hysteretic, and the area of hysteresis loop becomes ...

Continual scaling of the CMOS technology requires thinner gate dielectric to maintain high performance. However, when moving into the sub-45 nm CMOS generation, the traditional poly-Si gate approach cannot effectively reduce the gate thickness further due to the poly-depletion effect. Fully silicided Ni metal gate (FUSI) has been proven to be a promising solution. Ni FUSI metal gate can signifi...

Ambipolar polymeric field-effect transistors can be programmed into a p- or n-type mode by using the remanent polarization of a ferroelectric gate insulator. Due to the remanent polarity, the device architecture is suited as a building block in complementary logic circuits and in CMOS-compatible memory cells for non-destructive read-out operations.

The two-dimensional electron gas charge-coupled device (ZDEG-CCD) structure for 111-V and other heterojunction materials is reviewed. Device design considerations for gate, insulator, and channel material parameters are presented. Optimization of ZDEG-CCD performance parameters such as well capacity, dark current, and transfer efficiency is discussed. Experimental results on AIGaAs/GaAs uniform...

Recently, AlN plasma-enhanced atomic layer deposition (ALD) passivation technique had been proposed and investigated for suppressing the dynamic on-resistance degradation behavior of high-electron-mobility transistors (HEMTs). In this paper, a novel gate dielectric and passivation technique for GaN-on-Si AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MISHEMTs) is pr...

Solution-processed gate dielectrics were fabricated with the combined ZrO2 and Al2O3 (ZAO) in the form of mixed and stacked types for oxide thin film transistors (TFTs). ZAO thin films prepared with double coatings for solid gate dielectrics were characterized by analytical tools. For the first time, the capacitance of the oxide semiconductor was extracted from the capacitance-voltage propertie...